International Business Machines Corporation

Javier Ayala

Eric Peter Solecky

Marc J Postiglione

Christian Lavoie

Ahmet Serkan Ozcan

A method of forming a semiconductor device includes forming a silicide contact region of a field effect transistor (FET); forming a shallow impurity region in a top surface of the silicide contact region; and forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.

Silicided device with shallow impurity regions at interface between silicide and stressed liner

A system and method for optimizing and implementing a metrology sampling plan. A system is provided that includes a system for collecting historical metrology data from a metrology tool; and a reduction analysis system that compares an initial capability calculated from the historical metrology data with a recalculated capability for a reduced data set, wherein the reduced data set is obtained by removing a subset of data from the historical metrology data.

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Poughkeepsie, NY, United States of America

Javier Ayala