Analog Devices,inc.

Analog Devices International Unlimited Company

Analog Devices Global

Analog Devices Global Unlimited Company

Javier Alejandro Salcedo

Srivatsan Parthasarathy

David J Clarke

James Zhao

Patrick Martin McGuinness

David Aherne

John Anthony Cleary

Linfeng He

Alan J O'Donnell

Gavin Patrick Cosgrave

Shuyun Zhang

Albert C O'Grady

Jonathan Pfeifer

Juan Luo

Graham McCorkell

Karl Sweetland

David Casey

Michael C Coln

David Hall Whitney

Stephen Denis Heffernan

Kieran K Heffernan

John Twomey

Rodrigo Carrillo-Ramirez

Alan Righter

Yuhong Huang

Brian B Moane

Miguel Chanca

Jean-Jacques Hajjar

Colin B McHugh

Lejun Hu

Yuanzhong Zhou

Andrew Lewine

Enrique C Bosch

Seamus Murnane

A Paul Brokaw

Padraig Fitzgerald

Jeffrey G Barrow

Franklin Marshall Murden, Ii

Ralph David Moore, Jr

Sandro Herrera

Brian Anthony Moane

Evgueni Vladimirovich Ivanov

Colm Donovan

Peter Delos

Michael Lynch

Stephan Goldstein

Chiong Yew Lai

John P Guido

Sirui Luo

Todd Thomas

Paul Cheung

Jonathan Glen Pfeifer

Alan J O′Donnell

Tom Pilling

Albert C O′Grady

Minsheng Li

Alan J O'DONNELL

Albert C O'GRADY

John A Cleary

Patrick Martin Mcguinness

Low capacitance silicon controlled rectifier (SCR) topologies for overvoltage protection are disclosed herein. In certain embodiments, an overvoltage protection circuit is connected between an RF signal pad and a ground signal pad. The overvoltage protection circuit includes a fin field-effect transistor (FinFET) SCR including a PNP bipolar transistor and an NPN bipolar transistor that are cross-coupled, a FinFET trigger circuit connected between an emitter of the PNP bipolar transistor and a base of the NPN bipolar transistor, and a linearity enhancement impedance connected between a reference voltage terminal and the emitter of the PNP bipolar transistor. In certain implementations, a FinFET diode is further included in series with the FinFET SCR with a cathode of the FinFET diode connected to the emitter of the PNP bipolar transistor.

Low capacitance silicon controlled rectifier topology for overvoltage protection

Fin field-effect transistor (FinFET) thyristors for protecting high-speed communication interfaces are provided. In certain embodiments herein, high voltage tolerant FinFET thyristors are provided for handling high stress current and high RF power handling capability while providing low capacitance to allow wide bandwidth operation. Thus, the FinFET thyristors can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, while addressing tight radio frequency design window and robustness. In certain implementations, the FinFET thyristors include a first thyristor, a FinFET triggering circuitry and a second thyristor that serves to provide bidirectional blocking voltage and overstress protection. The FinFET triggering circuitry also enhances turn-on speed of the thyristor and/or reduces total on-state resistance.

FinFET thyristors with embedded transistor control for protecting high-speed communication systems

Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Systems and methods for charge storage and providing power

Monolithic microwave integrated circuits (MMICs) tolerant to electrical overstress are provided. In certain embodiments, a MMIC includes a signal pad that receives a radio frequency (RF) signal, and an RF circuit coupled to the RF signal pad. The RF circuit includes a transistor layout, an input field-effect transistor (FET) implemented using a first portion of a plurality of gate fingers of the transistor layout, and an embedded protection device electrically connected between a gate and a source of the input FET and implemented using a second portion of the plurality of gate fingers. The MMIC is tolerant to electrical overstress events, such as field-induced charged-device model (FICDM) events.

Monolithic microwave integrated circuits tolerant to electrical overstress

Electrical overstress protection for high speed interfaces are disclosed. In certain embodiments, a semiconductor die with bidirectional protection against electrical overstress is provided. The semiconductor die includes a first pad, a second pad, a forward protection silicon controlled rectifier (SCR) electrically connected between the first pad and the second pad and configured to activate in response to electrical overstress that increases a voltage of the first pad relative to a voltage of the second pad, and a reverse protection SCR electrically connected in parallel with the forward protection SCR between the first pad and the second pad and configured to activate in response to electrical overstress that decreases the voltage of the first pad relative to the voltage of the second pad.

Electrical overstress protection with low leakage current for high voltage tolerant high speed interfaces

Herein disclosed are systems and circuitry for protecting against overdrive and electrostatic discharge. For example, protection circuitry may include field effect transistors to discharge overdrive outside of an operational voltage range of a circuit in some embodiments to prevent damage to the circuit. Further, the protection circuitry may utilize diode features inherent in the field effect transistors to protect against electrostatic discharge in some embodiments. The circuitry may be implemented in radio frequency sampling analog-to-digital converters and can provide for single-ended signal input and/or output for the analog-to-digital converters.

Electrostatic discharge and overdrive protection circuitry

Charge storage with electrical overstress protection

FinFET thyristors for protecting high-speed communication interfaces

High voltage clamps with transient activation and activation release control are provided herein. In certain configurations, an integrated circuit (IC) includes a clamp electrically connected between a first node and a second node and having a control input. The IC further includes a first resistor-capacitor (RC) circuit that activates a detection signal in response to detecting a transient overstress event between the first node and the second node, an active feedback circuit that provides feedback from the first node to the control input of the clamp in response to activation of the detection signal, a second RC circuit that activates a shutdown signal after detecting passage of the transient overstress event based on low pass filtering a voltage difference between the first node and the second node, and a clamp shutdown circuit that turns off the clamp via the control input in response to activation of the shutdown signal.

High voltage clamps with transient activation and activation release control

Microwave amplifiers tolerant to electrical overstress are provided. In certain embodiments, a monolithic microwave integrated circuit (MMIC) includes a signal pad that receives a radio frequency (RF) signal, a ground pad, a balun including a primary section that receives the RF signal and a secondary section that outputs a differential RF signal, an amplifier that amplifies the differential RF signal, and a plurality of decoupling elements, some of them electrically connected between the primary section and the ground pad, others electrically connected in the secondary section to a plurality of the amplifier's nodes, and operable to protect the amplifier from electrical overstress. Such electrical overstress events can include electrostatic discharge (ESD) events, such as field-induced charged-device model (FICDM) events, as well as other types of overstress conditions.

Microwave amplifiers tolerant to electrical overstress

Electrical overstress protection for high speed applications is provided. In certain embodiments, a method of distributed and customizable electrical overstress protection for a semiconductor die is provided. The method includes configuring a heterogeneous overstress protection array that includes a customizable forward protection circuit electrically connected between a power high pad, a power low pad, and a signal pad and distributed across the semiconductor die, including selecting a number of segmented overstress protection devices from a plurality of available overstress protection devices of the customizable protection circuit. The method also includes choosing a device type of the selected segmented overstress protection devices from amongst two or more different device types providing complementary protection characteristics and protecting a core circuit from electrical overstress using the selected segmented overstress protection devices, the core circuit electrically connected to at least the signal pad, the power high pad, and the power low pad.

Distributed electrical overstress protection for large density and high data rate communication applications

High voltage tolerant electrical overstress protection with low leakage current and low capacitance is provided. In one embodiment, a semiconductor die includes a signal pad, an internal circuit electrically connected to the signal pad, a power clamp electrically connected to an isolated node, and one or more isolation blocking voltage devices electrically connected between the signal pad and the isolated node. The one or more isolation blocking voltage devices are operable to isolate the signal pad from a capacitance of the power clamp. In another embodiment, a semiconductor die includes a signal pad, a ground pad, a high voltage/high speed internal circuit electrically connected to the signal pad, and a first thyristor and a second thyristor between the signal pad and the ground pad.

Electrical overstress protection for electronic systems subject to electromagnetic compatibility fault conditions are provided herein. In certain implementations, a stacked thyristor protection structure with a high holding voltage includes a protection device having a trigger voltage and a holding voltage. A trigger voltage of the stacked thyristor protection structure is substantially equal to the trigger voltage of the protection device. The stacked thyristor protection structure further includes at least one resistive thyristor electrically connected to the protection device and operable to increase a holding voltage of the stacked thyristor protection structure relative to the holding voltage of the protection device. The at least one resistive thyristor comprising a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and a conductor connecting a collector of the PNP bipolar transistor to a collector of the NPN bipolar transistor.

Electrical overstress protection for electronic systems subject to electromagnetic compatibility fault conditions

A semiconductor die with high-voltage tolerant electrical overstress circuit architecture is disclosed. One embodiment of the semiconductor die includes a signal pad, a ground pad, a core circuit electrically connected to the signal pad, and a stacked thyristor protection device. The stacked thyristor includes a first thyristor and a resistive thyristor electrically connected in a stack between the signal pad and the ground pad, which enhances the holding voltage of the circuit relatively to an implementation with only the thyristor. Further, the resistive thyristor includes a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and an electrical connection between a collector of the PNP bipolar transistor and a collector of the NPN bipolar transistor. This allows the resistive thyristor to exhibit both thyristor characteristics and resistive characteristics based on a level of current flow.

High voltage tolerant circuit architecture for applications subject to electrical overstress fault conditions

Storing charge associated with electrical overstress

Growing community of inventors

North Billerica, MA, United States of America

Javier Alejandro Salcedo