Unisys Corporation

Javesh Vrajlal Sheth

Theodore C White

A computer architecture where a processor with store-through cache is linked with a cache control module, a bus interface to dual system busses, a system spy module monitoring the dual system busses for new data overwrites and an invalidation queue for holding cache addresses to be invalidated while the entire network is controlled by a programmable state machine system for enabling cache access and cache invalidation operations.

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Mission Viejo, CA, United States of America

Javesh Vrajlal Sheth