Intel Corporation

Vefxi Corporation

Javed Sabir Barkatullah

Nasser A Kurd

Thomas D Fletcher

Chakrapani Pathikonda

Vivek K De

James W Tschanz

Matthew A Fisch

Siva G Narendra

Edward Allyn Burton

Eitan E Rosen

Keng L Wong

Tim Frodsham

Douglas M Carmean

David J O'Brien

Paul D Madland

Tawfik M Rahal-Arabi

Hung-Piao Ma

Charles E Dike

R Kenneth Hose

Rommel O Dizon

A method for adjusting and generating enhanced 3D-effects for 2D to 3D image and video conversion applications includes controlling a depth location of a zero parallax plane within a depth field of an image scene to adjust parallax of objects in the image scene, controlling a depth volume of objects in the image scene to one of either exaggerate or reduce 3D-effect of the image scene, controlling a depth location of a segmentation plane within the depth field of the image scene, dividing the objects in the image scene into a foreground group and a background group, selectively increasing or decreasing depth volume of objects in the foreground group, selectively increasing or decreasing depth separation of objects in the foreground group relative to the objects in the background group, and generating an updated depth map file for a 2D-image.

Method and apparatus for generating enhanced 3D-effects for real-time and offline applications

A method for converting a 2D images and videos to 3D includes applying a set of pre-defined heuristic rules to assign a depth value for each pixel of a two-dimensional (2D) image source based on pixel attributes to generate an initial default depth map, refining the pre-defined heuristic rules to produce customized heuristic rules, applying the customized heuristic rules to the initial default depth map to produce a refined depth map, and rendering a three-dimensional (3D) image in a predefined format using the refined depth map.

Method and apparatus for converting 2D-images and videos to 3D for consumer, commercial and professional applications

A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.

Apparatus for power consumption reduction

In some embodiments, a PLL with an output to provide a PLL output clock at a target frequency is provided. The PLL comprises a VCO to generate a clock to be used to generate the PLL output clock. Also provided is circuitry to maintain the VCO's bias level at a sufficient level if it is insufficient. Other embodiments may be disclosed herein.

PLL with controlled VCO bias

Apparatus and systems, as well as methods and articles, may operate to select a microprocessor clock frequency responsive to a desired voltage and/or a desired temperature of operation.

Frequency management apparatus, systems, and methods

On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Method and apparatus for detecting on-die voltage variations

A circuit for generating and distributing highly accurate and stable clocks on a large integrated die is described. A Digital De-skew System is used to help prevent metastability and dither, provide a wide controllable delay range, and alternate sampling of phase detectors.

Circuit to manage and lower clock inaccuracies of integrated circuits

Method for power consumption reduction

A clock generating apparatus is provided that includes a first phase lock loop device powered by an analog (or fixed) power supply voltage and a second phase lock loop device powered by the analog power supply voltage and a digital power supply voltage. The second phase lock loop device to output a clock signal having an adaptive frequency based on the digital power supply voltage.

Adaptive frequency clock generation system

Transistor bodies are biased to modify delay in clock buffers.

Adaptive body bias for clock skew compensation

A clock duty cycle correction circuit. The duty cycle correction circuit is provided at a receiver in a clock distribution network to correct a duty cycle of a distributed clock signal.

Smart buffer circuit to match a delay over a range of loads

A method and apparatus for optimizing clock distribution in a circuit to reduce the effect of power supply noise. Parameters are determined including: a response curve of a power source for a circuit, a delay sensitivity of a clock net in the circuit to the power source, a delay sensitivity of a data net in the circuit to the power source, a data delay for the data net, and a clock delay for the clock net. The clock delay is adjusted to reduce the effect of power supply noise on the data net. The adjusting is based on the response curve of the power source, the delay sensitivity of the clock net, the delay sensitivity of the data net, the data delay, and the clock delay. The adjusting includes adding a pre-distribution clock delay.

Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise

According to some embodiments, a clock signal having an adaptive frequency is provided.

Adaptive frequency clock signal

According to some embodiments, a plurality of ring oscillators are associated with a generation and/or distribution of a clock signal.

Growing community of inventors

Portland, OR, United States of America

Javed Sabir Barkatullah