Texas Instruments Corporation

Other

Jau-Yuann Yang

Donald L Plumton

Han-Tzong Yuan

Francis J Morris

Rajni J Aggarwal

Tae S Kim

Zhiqiang (Jeff) Wu

Taylor R Efland

Louis N Hutter

Kaiping Liu

Gregory A Magel

Antonio Luis Pacheco Rotondaro

John P Erdeljac

Shaoping Tang

John Kenneth Arch

Jeffrey P Smith

Albert H Taddiken

C Matthew Thompson

Terrance Gus McDonald

Mary Ann Murphy

Hamseswari Renganathan

Donald L Plumpton

An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.

High sheet resistor in CMOS flow

In one embodiment, a method for extracting C-V characteristics of ultra-thin oxides includes coupling a device under test to a testing structure, in which the device under test includes a plurality of transistors. Alternatively, the device under test includes a plurality of varactors. The method further includes inputting a radio frequency signal of at least one GHz into the testing structure, de-embedding the parasitics of the testing structure, inputting a bias into the device under test, determining the capacitance density per gate width of the device under test, plotting capacitance density per gate width versus gate length to obtain a first curve, and determining a slope of the first curve. These steps are repeated for one or more additional biasing conditions, and the determined slopes are plotted on a capacitance density per voltage graph to obtain a C-V curve for the device under test.

System and method for extraction of C-V characteristics of ultra-thin oxides

Methods are provided for forming wells in a semiconductor wafer, in which p-wells and n-wells are formed in a substrate, and first p-type dopants are implanted into n-well regions while an n-well mask remains over the wafer to selectively decrease a substrate resistivity in the n-well regions beneath the n-wells. A subsequent blanket implantation provides second p-type dopants into isolation regions of the substrate beneath isolation structures, where the first and second p-type dopants improve well to well isolation without addition of extra masks to the fabrication process.

Methods for improving well to well isolation

A power field effect transistor is disclosed that includes polysilicon gate bodies (,) and (,), which includes platinum silicide contact layers (,) and (,) disposed on the outer surfaces of bodies (,) and (,), respectively. In addition, the device comprises an n&plus;drain region (,) which also has a platinum silicide drain contact layer (,) formed on its outer surface and platinum silicide source contact layers (,) and (,). During formation, sidewall spacers (,) and (,), as well as mask bodies (,) and (,) are used to ensure that platinum silicide layer (,) spaced apart from both gate bodies (,) and (,) and platinum silicide gate contact layers (,) and (,).

Power transistor with silicided gate and contacts

A vertical transistor (70) comprising a first semiconductor layer (14) of a first conductive type. A gate structure (32) of a second conductive type disposed on the first semiconductor layer (14). The gate structure (32) may include a plurality of gates (38) separated by channels (40). A second semiconductor layer (50) of the first conductive type may be disposed over the gate structure (32) and in the channels (40). An arresting element (36) may be disposed between and upper surface of the gates (38) and the second semiconductor layer (50). A void (52) may be formed in the second semiconductor layer (50) over the gate (38).

Vertical transistor and method

A method and structure for a vertical FET transistor device (VFET) is described for a lower junction capacitance VFET to decrease the switching power loss and achieve increased current capacity and/or deceased thermal dissipation. In a preferred embodiment, the gate capacitance is reduced over prior art methods and structures by etching to the gate 14 and directly contacting the p+ gate with a p-ohmic contact 24. In another embodiment, the area under the gate contact 22 is implanted with a 'trim' dopant, where the trim dopant acts to reduce the doping of the drainlayer thereby reducing the capacitance. In another embodiment, the area under the exposed gate contact 22 is isolated by ion damaged to reduce the doping/conductivity of the n- drain layer below a portion of the gate layer to reduce the gate-to-drain capacitance.

Low capacitance power VFET method and device

A voltage regulator (10) comprising a vertical channel transistor (12). The vertical channel transistor (12) may have a gate (16), a voltage input terminal (18), and a voltage output terminal (20). A reference voltage supply (14) may be coupled to the gate (16).

Integrated voltage regulator circuit with vertical transistor

An optical device for sensing properties in an environment such as the presence of a substance or chemical in the zone to be monitored using optical components integrated on a microchip base or substrate. A preferred embodiment introduces a method for fabricating a miniature microchip chemical sensor by integrating a GaAs LED 14 with a polyimide waveguide 48 and a silicon photosensor 16 on the same chip. Light 18 is emitted at the edge of the GaAs LED 14. A portion of the light propagates is detected by a PIN diode 16. A chemical sensitive material 50 is coated on top of a polyimide waveguide 48. When the gas or chemical to which the material is sensitive appears, the light transmitted from the polyimide to air increases, thus the total signal sensed by the photodetector decreases, whereby the change in light signal indicates detection.

Integrated microchip chemical sensor

A method and structure is given for flip-chip mounting an integrated circuit on a substrate. An embodiment of the present invention is a GaAs die flip-chip 14 mounted to a silicon semiconductor 10 which has additional processing circuitry. The flip-chip bond uses an alloy metal film, preferably a thin film of AuGe 38, 40. The invention gives a high temperature bond which is suitable for subsequent high temperature processes to be performed on the flip-chip mounted combination. The bond may also include a diffusion barrier 36 which provides a short circuit free LED contact. A preferred embodiment introduces a microchip chemical sensor by integrating a GaAs LED 14 with a polyimide waveguide 56 and a silicon photosensor 16 on the same chip.

Flip-chip die attachment for a high temperature die to substrate bond

A self-aligned planar heterojunction bipolar transistor (10) is fabricated by forming a base layer (18) and forming an emitter layer (20) on the base layer (18). An emitter cap layer (22) is formed on the emitter layer (20) and an interface layer (24) is formed on the emitter cap layer (22). A first implantation layer (26) is formed through the interface layer (24), the emitter cap layer (22), and the emitter layer (20) to the base layer (18). A second implantation layer (30) is formed through the interface layer (24), the emitter cap layer (22), and the emitter layer (20) to the base layer (18) and overlaps the first implantation layer (26). A portion of the interface layer (24), the emitter cap layer (22), and the implantation layers (26, 30) are removed and replaced by an insulating region (33). An emitter contact (38) is formed on the remaining emitter cap layer (22) and is isolated from the implantation layers (26, 30) by the insulating region (33). The insulating region (33) acts as a buffer to self-align the emitter contact (38) to the implantation layer (26, 30).

Method of self-aligning an emitter contact in a planar heterojunction

A method of self aligning an emitter contact includes forming a base layer (18) on a portion of a collector layer (16). An interface layer (22) is formed on the base layer (18) such that a portion of the base layer (18) remains exposed. An emitter layer (24) is formed on the collector layer (16), the interface layer (22), and the exposed portion of the base layer (18). An emitter cap layer (26) is formed on the emitter layer (24) over the previously exposed area of the base layer (18). An insulating layer (28) is formed on the interface layer (22). An emitter contact (36) is formed on the emitter cap layer (26) at the previously exposed area of the base layer (18). The insulating layer (28) isolates the emitter contact (36) from the base layer (18) and a subsequently formed base contact (38). The insulating layer (28) ensures isolation between the emitter contact (36) and the base contact (38) despite misalignment of the emitter contact (36) during formation.

Bipolar transistor having a self emitter contact aligned

This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44. Other devices and methods are also disclosed.

Growing community of inventors

Richardson, TX, United States of America

Jau-Yuann Yang