Lsi Corporation

Lsi Logic Corporation

Nvidia Corporation

Jau-Wen Chen

William Loh

Choshu Ito

Yoon J Huh

Payman Zarkesh-Ha

Erhong Li

Roberto Sung

Minxuan Liu

Ken Doniger

Peter Bendix

A technique for providing electrostatic discharge (ESD) protection in complementary metal-oxide semiconductor (CMOS) technologies is disclosed. A power supply RC-based ESD protection circuit having an RC value in the nanosecond range increases the allowable power-up slew rate so that fast power-up events (e.g., hot-plug and power switching operations) are not erroneously interpreted as ESD events. Because the RC value is small, the layout area needed for the RC-based ESD protection circuit is also reduced.

Electrostatic discharge protection circuit having high allowable power-up slew rate

A technique for enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process

A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

A system and method for protecting a circuit. The system includes a protection circuit that includes an inverter and a capacitor coupled to the inverter. The inverter and the capacitor are implemented using logic circuits of a circuit core, and the inverter shunts electrostatic discharge ESD current through the capacitor. According to the system and method disclosed herein, because the protection circuit shunt circuit shunts ESD current using logic circuits of the circuit core, ESD protection is achieved while not requiring large FETs. Also, the protection circuit protects circuits against ESD events that conventional FET cannot protect.

Circuit protection system

A silicon-controlled rectifier apparatus, comprising a substrate upon which a low-voltage triggered silicon-controlled rectifier is configured. A plurality of triggering components (e.g., NMOS fingers) are formed upon the substrate and integrated with the low-voltage triggered silicon-controlled rectifier, wherein the plurality of triggering components are inserted into the low-voltage triggered silicon-controlled rectifier in order to permit the low-voltage triggered silicon-controlled rectifier to protect against electrostatic discharge during human-body model and charged-device model stress events.

Design of silicon-controlled rectifier by considering electrostatic discharge robustness in human-body model and charged-device model devices

An improvement to a digital integrated circuit of the type having a functional circuit that is susceptible to damage from an electrostatic discharge. An electrostatic discharge protection element is placed in series with the functional circuit and disposed upstream in a normal direction of current flow from the functional circuit. The electrostatic discharge protection element includes at least one of a resistive choke that exhibits thermal runaway and an inductive choke.

Electrostatic discharge series protection

An electrostatic discharge protection circuit adapted to reduce an electrostatic discharge event on a line of an integrated circuit. The protection circuit includes an NMOS transistor having a source contact that is electrically connected to the line. A drain contact is electrically connected to a logical low voltage, and a gate contact is also electrically connected to the logical low voltage, through a resistor. A substrate bias pump is electrically connected to a back gate of the NMOS transistor, where the bias pump provides a steady state direct current negative bias during normal operation of the integrated circuit when there is no electrostatic discharge event.

Bias for electrostatic discharge protection

The present invention provides a system and method for electrostatic discharge (ESD) testing. The system includes a circuit that has a switch coupled to an input/output (I/O) circuit of a device under test (DUT), a charge source coupled to the switch, and a control circuit coupled to the switch, wherein the control circuit turns on the switch to discharge an ESD current from the charge source to the I/O circuit, and wherein the circuit is integrated into the DUT. According to the system and method disclosed herein, the system provides on-chip ESD testing of a DUT without requiring expensive and specialized test equipment.

Electrostatic discharge testing

Design and optimization of NMOS drivers using a self-ballasting ESD protection technique in a fully silicided CMOS process. Silicided NMOS fingers which include segmented drain diffusion. Specifically, the segmented drain diffusion provides self-ballasting resistors which improves the ESD performance. Preferably, the width of the each diffusion resistor is relatively small, as this can improve a non-uniform silicidation process. The resistance of the segmented diffusion resistors is determined by their width and length, and effectively increases the ballasting effect of parasitic n-p-n bipolar transistors.

Optimization of NMOS drivers using self-ballasting ESD protection technique in fully silicided CMOS process

An implantation method to improve ESD robustness of thick-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies. Based on standard process flow in DGO, a thick gate-oxide ESD device is improved. Instead of using the standard I/O device, the ESD device uses the thin-oxide N-LDD implantation, and thus its ESD robustness is enhanced. This is performed by updating the logic Boolean operations of thick gate-oxide and thin gate-oxide N-LDD before fabricating the masks. In TGO, the intermediate-oxide ESD uses thin-oxide N-LDD implantation, and the thick-oxide ESD uses intermediate-oxide N-LDD implantation.

Implantation method to improve ESD robustness of thick gate-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies

A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process

Fabricated using a complementary metal oxide semiconductor process including the use of salicides, an input and power protection circuit for use in an integrated circuit protects voltage and signal terminals from both overvoltage and ESD pulses. A diode connected is connected between a first terminal and an inter-transistor node, a field effect transistor is connected between the inter-transistor node and a second terminal, and a lateral bipolar transistor, with a base connected to the inter-transistor node, is connected between the first and the second terminals. When an ESD pulse appears on the first terminal, the voltage at the inter-transistor node increases until a snapback trigger voltage of the field effect transistor is reached whereupon current flows from the first terminal, through the emitter-base junction of the lateral bipolar transistor, through the inter-transistor node, through the field effect transistor, and to the second terminal. In response to the current flow through the inter-transistor node, the lateral bipolar transistor substantially increases the current flow from the first terminal, through the lateral bipolar transistor, and to the second terminal so that a majority of current will flow through this path. Similarly, when an ESD pulse appears on the second terminal, this creates current flow from the second terminal, through the collector-base junction of the lateral bipolar transistor, through the inter-transistor node, through the diode, and to the first terminal.

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Cupertino, CA, United States of America

Jau-Wen Chen