United Microelectronics Corp.

United Integrated Circuits Corp.

Jau-Hone Lu

Shu-Ying Lu

Chang-Ming Lu

Wunn-Shien Liao

Ya-Ling Hung

Ching-ming Lee

A method of fabricating a contact window of a semiconductor device is described in which a conductive layer is used to cover the boundary of the neighboring isolation structure of the source/drain region, or to also cover the source/drain region. An insulation layer is formed on the entire substrate. The insulation layer is then defined to form a contact window, exposing the source/drain region or exposing the conductive layer located on top of the source/drain region.

Method of fabricating a contact window

The present invention relates to a method of fabricating a DRAM capacitor. As the capability of the charges stored in the capacitor is in proportion to the area of the capacitor plates, the electrodes of the DRAM capacitor according to the present invention is bowl-shaped such that the area of the capacitor increases. Further, the process is simple, and the height of the bowl-shaped capacitor is not as large as that of the conventional capacitor.

Method for fabricating a DRAM capacitor

A method for manufacturing a capacitor of a mixed-mode circuit. A substrate is provided. An isolation region is formed on the substrate to define an active region in the substrate. An oxide layer, a first polysilicon layer and a first silicide layer are formed over the substrate. The oxide layer, the first polysilicon layer and the first silicon layer are patterned to form a gate structure on the active region and to form a first polysilicon electrode and a first silicide electrode on the isolation region. A dielectric layer is formed over the substrate. An opening is formed to expose a portion of the first silicide electrode. A second silicide layer is formed on a sidewall and a bottom of the opening and on the dielectric layer. A planarization process is performed to remove a portion of the second silicide layer above the dielectric layer, wherein the remaining second silicide layer in the opening, the silicide electrode and the polysilicon electrode together form a bottom electrode of the capacitor. A capacitor dielectric layer is formed over the substrate. A first metal layer is formed over the substrate. The first metal layer is patterned to form an upper electrode of the capacitor.

Method for manually manufacturing capacitor

A method is provided to increase the contact area of a contact window. In this method, the contact area is mainly increased by a concavity which is formed by first forming a thin oxide layer in the contact region using local oxidation, then further by removing the thin oxide layer. Additionally, in order to reduce the contact resistance, a metal oxide layer can be selectively formed at the contact interface.

Method of increasing contact area of a contact window

An improved dual damascene process is provided. By a spacer formed on sidewalls of an oxide layer, the method can make a via plug and a metal layer serving as an interconnect simultaneously form in a self-aligned process. Therefore, it can successfully avoid misalignment while forming a via plug and an interconnect.

Dual damascene

A method for fabricating a mixed-mode device. A first gate oxide layer and a second gate oxide layer are formed. The polysilicon layer is used as a mask to pattern the gate oxide layers. Additionally, a top electrode is formed during the first gate oxide layer is patterned. A bottom electrode is formed during the second gate oxide layer is patterned. The first gate oxide layer and the second gate oxide layer are formed by a single oxidation operation, thus thicknesses of the first gate oxide layer and the second oxide layer can be effectively controlled.

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Hsinchu Hsien, Taiwan

Jau-Hone Lu