Arm Limited

Jatin Bhartia

Antony John Penton

Kauser Yakub Johar

Yasuo Ishii

Houdhaifa Bouzguarrou

Michael Brian Schinzler

Eric Ola Harald Liljedahl

Adrian Viorel Popescu

Remus-Gabriel Vultur

Sumanth Chengad Raghu

An apparatus with an additional storage element or field is provided where a subscription indicator is stored, indicating a subscription to a region of memory, and hence subscribing to a cache line corresponding to the region of memory. In response to a subscribed cache line being invalidated, the apparatus performs actions to re-fetch the cache line, and to store the cache line in the cache after a short delay. The subscription indicator may be stored in a variety of ways, and may include further information that influences the functionality of the present techniques. Such further information may be adjustable in order to dynamically control the functionality of the disclosed techniques for a particular implementation over time.

Cache line subscription

A first type of prediction, for controlling execution of at least one instruction by processing circuitry, is based at least on a first prediction table storing prediction information looked up based on at least a first portion of branch history information stored in branch history storage corresponding to a first predetermined number of branches. In response to detecting an execution state switch of the processing circuitry from a first execution state to a second, more privileged, execution state, use of the first prediction table for determining the first type of prediction is disabled. In response to detecting that a number of branches causing an update to the branch history storage since the execution state switch is greater than or equal to the first predetermined number, use of the first prediction table in determining the first type of prediction is re-enabled.

Re-enabling use of prediction table after execution state switch

Aspects of the present disclosure relate to an apparatus comprising fetch circuitry. The fetch circuitry comprises a pointer-based fetch queue for queuing processing instructions retrieved from a storage, and pointer storage for storing a pointer identifying a current fetch queue element. The apparatus comprises decode circuitry having a plurality of decode units, and fetch queue extraction circuitry to, based on the pointer, extract the content of a plurality of elements of the fetch queue; apply combinatorial logic to speculatively produce, from the content of said fetch queue entries, a plurality of speculative potential instructions; and transmit each speculative potential instruction to a corresponding one of said decode units. Each decode unit is configured to decode the corresponding speculative potential instruction. The instruction extraction circuitry is configured to extract a subset of said plurality of speculative potential instructions, and transmit said determined subset to pipeline component circuitry.

Speculative usage of parallel decode units

A processing systemincludes a processing pipelinewhich includes fetch circuitryfor fetching instructions to be executed from a memory. Buffer control circuitryis responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry), to accumulate within one or more buffersfetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.

Programmable instruction buffering for accumulating a burst of instructions

A processing system includes a processing pipeline which includes fetch circuitry for fetching instructions to be executed from a memory. Buffer control circuitry is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry), to accumulate within one or more buffers fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.

Programmable instruction buffering of a burst of instructions including a pending data write to a given memory address and a subsequent data read of said given memory address

Growing community of inventors

Cambridge, United Kingdom

Jatin Bhartia