International Business Machines Corporation

Jatin Bhartia

Matthias D Heizmann

Narasimha R Adiga

Akash V Giri

Parminder Singh

Ajit S Honnungar

Anthony Saporito

James J Bonanno

Khary J Alexander

Adam B Collura

Jane Helen Bartik

James R Mitchell

Jang-Soo Lee

Embodiments include a method for verifying a counter design within a tolerance window within which a race condition occurs between a context event and a design event. The method includes receiving a plurality of events within the counter design, the plurality of events including the context event and the design event. The method also includes dynamically determining the tolerance window around the context event by setting a first portion of the tolerance window to precede an occurrence of the context event and by setting a second portion of the tolerance window to follow the context event. Additionally, the method includes performing a verification of whether the design event is within the first portion of the tolerance window or the second portion of the tolerance window.

Robust and adaptable management of event counters

A method comprises identifying a number of branches (N) and a number of iterations (N) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals N, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than N&#x2212;1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than N, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.

Pattern based branch prediction

Embodiments relate to testing memory write operations. An aspect includes detecting a first write operation to a set of 'n' divisions in a memory table, and defining a selected set of entries of an optimization checking table corresponding to the set of 'n' divisions of the memory table. The aspect includes determining that at least one selected entry of the selected set of entries is not among an optimal set of entries of the checking table. The aspect further includes determining whether to generate an optimization error or to end an optimization analysis of the first write operation without generating the optimization error by comparing the first time stamps of one or both of the at least one selected entry and one or more optimal entries of the optimal set of entries to a temporal window defined by a predetermined duration.

Testing optimization of microprocessor table functions

Embodiments include a method, system, and computer program product for verifying a counter design. A method includes receiving a plurality of events within the counter design. The plurality of events can include a context event and a design event. The method also includes determining a tolerance window in response to the receiving of the context. The tolerance window is defined around the context event and includes a first portion before an occurrence of the context event and a second portion after the context event. The method further includes performing a verification algorithm to identify whether the design event is within the tolerance window and should be accounted for by a design model counter of the counter design.

Technical solutions are described for dynamically managing an operand-store-compare (OSC) prediction table for load and store operations executed out-of-order. One general aspect includes a method that includes receiving a request to retire a queue entry corresponding to an instruction. The method also includes identifying an OSC prediction for the instruction based on an OSC prediction table entry, where the OSC prediction indicates if the instruction is predicted to hit an OSC hazard. The method also includes determining if the instruction hit the OSC hazard. The method also includes in response to the OSC prediction indicating that the instruction is predicted to hit the OSC hazard and the instruction not hitting the OSC hazard, invalidating the OSC prediction table entry corresponding to the instruction. The present document further describes examples of other aspects such as methods, computer products.

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Uttar Pradesh, India

Jatin Bhartia