Motorola Corporation

Jaswinder S Jandu

John M Pigott

Ira G Miller

Trevor S Smith

A method (701-717) and apparatus for providing a driver system requiring a reduced number of amplifier circuits. Load driving circuitry (205) is configured to include a single loop amplifier (401) for sequentially receiving multiplexed signals representative of the parameter values and effecting the output of such signals to corresponding loads. Sample-and-hold circuitry is coupled between the output of the loop amplifier (401) and load circuitry within the driver circuits (409, 429, 435) in an arrangement such that only one loop amplifier (401) is required in a multiplexed multi-input system.

Multiplexed driver system requiring a reduced number of amplifier

A waveform shaping circuit (120) provides a shaped variable pulse width modulation signal (VPWM) for an SAE (Society of Automotive Engineers) J1850 compliant bus. The J1850 specification defines a single wire multiplexed bus protocol for an automotive application. A counter logic circuit (440) receives a variable pulse width modulation signal (VPWM) signal having unshaped rising and falling edges and a clock having a period smaller than a desired rise or fall time. The counter logic circuit (440) shapes the rising and falling edges of the VPWM signal by sequentially switching each of a variable weighted resistor string (410) to produce an unfiltered shaped VPWM signal. The unfiltered shaped VPWM signal is smoothed by a low pass filter (430) to produce a smoothed shaped VPWM signal.

Waveform shaping circuit for a multiplexed information bus transmitter

An integrated circuit (20) includes a low voltage inhibit (LVI) circuit (21) to protect an internal circuit (22) against losses in power supply voltage. The LVI circuit (21) includes primary (30) and secondary (35) LVI circuits. The primary LVI circuit (30) is a high-precision analog circuit which is selectively enabled when the secondary LVI circuit (35) senses that the power supply voltage is approaching a critical range. The primary LVI circuit (30) resets an internal circuit (22) of the integrated circuit (20) when it senses the power supply voltage falling below a critical level. Thus, the higher current primary LVI circuit (30) need only be enabled when a more precise power supply voltage measurement is required. The LVI circuit (21) also includes a disabling circuit (40) which latches an active output of the primary LVI circuit (30) and then disables the primary LVI circuit (30).

Low voltage inhibit circuit and integrated circuit using same

A combined multiple memory array is disclosed which includes at least two differing types of memory arrays located next to and aligned to one another. The individual memory cells of the differing memory arrays are designed wherein the x pitches may vary in order to allow the y pitches to be substantially equal. A common set of row decoders provide common wordline decoding to the differing memory arrays. The memory arrays need not have the same number of words or bits to share the common row decoders. The column decoders may be separate for each array to account for different word sizes. A common set of column decoders is possible with equal word lengths from each array. A significant savings in silicon area may be saved by combining the multiple arrays.

Combined multiple memories

An operational amplifier is provided having a null offset that may be digitally adjusted quickly and accurately. The operational amplifier includes a cascode current mirror in an output stage wherein a small portion of current in the cascode current mirror is diverted away into a digitally controlled current divider. The more current that is diverted away, the larger the differential voltage that is created between the inverting and noninverting inputs of the operational amplifier. The current is increased until the output of the operational amplifier switches from the positive supply voltage to the ground supply voltage or vise versa. Additionally, a compensation capacitor at the output of the operational amplifier is switched out of the circuit during adjustment to speed up the null offset adjustment. Because the current being adjusted is not directly at the inputs of the operational amplifier the common mode input range is not deteriorated.

Operational amplifier having improved digitally adjusted null offset

A complementary voltage comparator is described wherein a CMOS operational amplifier having an input stage comprising N-channel field effect transistors is coupled with a CMOS operational amplifier having an input stage comprising P-channel field effect transistors. The outputs of the operational amplifiers are converted to currents and combined to indicate the relative magnitudes of the voltages being compared. This configuration allows the range of input voltages to vary over the full range of supply voltages and negates the need for offset correction.

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Mesa, AZ, United States of America

Jaswinder S Jandu