Intel Corporation

Jasper Balraj

Altug Koker

Daniel Nemiroff

Robert W Strong

Rajeev K Nalawadi

Sivakumar Radhakrishnan

Amber D Huffman

Sin Sim Tan

Bruce A Tennant

Jeffrey L Rabe

Geetani R Edirisooriya

John P Lee

In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed.

Dynamic squelch detection power control

A computer system provides a program access to a first register during real mode operation by using an index register and a data register, wherein the index register and the data register are located in real mode memory space and the first register is located outside of real mode memory space.

Index/data register pair for indirect register access

Growing community of inventors

Beaverton, OR, United States of America

Jasper Balraj