Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Jaspal Singh Shah

Atul Katoch

Sanjeev Kumar Jain

Manoj Sachdev

David Rennie

Sahil Preet Singh

Mohammad Sharifkhani

A memory device includes one or more memory cells, and a pipeline coupled to the one or more memory cells. The memory device includes a first pulse generator coupled to the one or more memory cells. The first pulse generator is configured to generate, based on a first delayed clock signal, a memory clock signal to control the one or more memory cells. The first delayed clock signal is delayed with respect to a clock signal. The memory device includes a second pulse generator to generate, based on a second delayed clock signal and the memory clock signal, a pipeline clock signal to provide data from the one or more memory cells through the pipeline. The second delayed clock signal is delayed with respect to the clock signal.

Circuits and methods of mitigating hold time failure of pipeline for memory device

A semiconductor device includes a memory bank and first and second clock generators. The first clock generator includes a first transistor configured to receive an external clock signal. The first clock generator is configured to generate a global clock signal that is based on the external clock signal and that controls writing to and reading from the memory bank. The second clock generator includes a first transistor configured to receive the external clock signal. The second clock generator is configured to generate a pipeline clock signal that is based on the external clock signal and that controls a pipeline operation of reading from the memory bank. Methods of operating the first and second clock generators are also disclosed.

Semiconductor device including first and second clock generators

In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.

Method, device, and circuit for high-speed memories

A memory device includes a memory array that includes one or more rows of memory cells and one or more columns of memory cells. The comparator circuitry is operably connected to at least one column of memory cells in the one or more columns of memory cells. The comparator circuitry includes a precompute circuit and a select circuit operably connected to the outputs of the precompute circuit. The precompute circuit is operable to precompute a comparison operation to produce a first precompute signal and a second precompute signal. The select circuit is operable to receive a first cell data signal from a memory cell in the column of memory cells. Based at least on the first cell data signal, the select circuit selects either the first precompute signal or the second precompute signal to output from the comparator circuitry as a signal read from the memory cell.

Memory device having a comparator circuit

A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.

Memory power management

A device is disclosed to include a memory cell, a first write assist unit and a second write assist unit. The first write assist unit provides a first operational voltage at a first pair of terminals of the memory cell. The second write assist unit provides at a second pair of terminals of the memory cell a second operational voltage different from the first operational voltage. In a write operation of the memory cell, the first write assist unit further generates a voltage difference between the first pair of terminals.

Write assist circuit of memory device

a device is disclosed to include a first write assist unit and a second write assist unit. The first write assist unit provides a first operational voltage and a second operational voltage to a memory cell. The second write assist unit provides a third operational voltage and a fourth operational voltage to the memory cell. During a write operation, the first write assist unit further adjusts the first operational voltage or the second operational voltage while the third operational voltage and the fourth operational voltage are at a same voltage level, and the second write assist unit further adjusts the third operational voltage or the fourth operational voltage while the first operational voltage and the second operational voltage are at a same voltage level.

A device including a memory cell is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The first inverter is operated with a first operational voltage and a third operational voltage, and the second inverter is operated with a second operational voltage and a fourth operational voltage. During a write operation of the memory cell, the first operational voltage and the second operational voltage are configured at different voltage levels, and the third operational voltage and the fourth operational voltage are configured at the same voltage level.

A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of an operational voltage provided to the first inverter or the second inverter by a bias voltage difference.

A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The first inverter is operated with a first operational voltage and a third operational voltage, and the second inverter is operated with a second operational voltage and a fourth operational voltage. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of the first operational voltage, the second operational voltage, the third operation voltage, the fourth operation voltage, or a combination thereof, by a bias voltage difference.

Sense amplifier configurations for memories are described. In these configurations, the differential inputs are boosted proportional to the respective bitline voltage enabling a low-voltage, reliable, faster sense amplifier operation. Disclosed sense amplifiers are also capable of compensating the threshold mismatch between the sensing transistors.

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Ottawa, Canada

Jaspal Singh Shah