Integrated Device Technology, Inc.

Jason Z Mo

Chi-Lie Wang

Mario F Au

Cheng-Han Wu

Bertan Tezcan

Calvin Nguyen

Ming-Shiung Chen

Kwong Hou Mak

Ta-Chung Ma

Xiaoping Fang

Lan Lin

Hui Su

A method and apparatus for congestion and fault management with time-to-live (TTL) have been disclosed. Each time a packet is transferred into an Egress Port's Final Buffer, an associated TTL Timeout Counter will be loaded with a value. If the packet cannot be transferred out of the Egress Port before TTL timeout, it will be purged by removing a memory buffer pointer from the corresponding Virtual Output Queue (VOQ) entry.

Method and apparatus for congestion and fault management with time-to-live

A method and apparatus for unified final buffer with pointer-based and page-based scheme for traffic optimization have been disclosed.

Method and apparatus for unified final buffer with pointer-based and page-based scheme for traffic optimization

A serial buffer transports packets through queues capable of operating in a packet mode or a raw data mode. In packet mode, entire packets are stored in a queue. In raw data mode, packet header/delimiter information is not stored in the queue (only packet data is stored). Packets can be transferred out of a queue in response to a slave read request. The serial buffer constructs a packet header in response to the slave read request, and retrieves a specified amount of packet data from the selected queue. The serial buffer also transfers out packets as a bus master when a water level exceeds a water mark within a queue. The serial buffer constructs packet headers for these bus master transfers, which may be performed in a flush mode or a non-flush mode (in packet mode), or in a flush mode (in raw data mode).

Method to support flexible data transport on serial protocols

A method and apparatus to optimize class of service under multiple VCs with mixed reliable transfer (RT) and continuous transfer (CT) modes have been disclosed where outstanding packets to be processed is through a Retransmission Mapper with a VOQ read pointer realignment that can quickly optimize network traffic with multiple VCs and mixed RT/CT modes.

Method and apparatus to optimize class of service under multiple VCs with mixed reliable transfer and continuous transfer modes

A method and apparatus for dynamic traffic management with packet classification have been disclosed where packet size, variation, and count may be used to select credit or packet based arbitration.

Method and apparatus for dynamic traffic management with packet classification

A method and apparatus for programmable buffer with dynamic allocation to optimize system throughput with deadlock avoidance on switches have been disclosed where a buffer availability is based on a programmable reservation size for dynamic allocation.

Method and apparatus for programmable buffer with dynamic allocation to optimize system throughput with deadlock avoidance on switches

A serial buffer includes a first port configured to operate in accordance with a first serial protocol and a second port configured to operate in accordance with a second serial protocol. A first translation circuit of the serial buffer allows packets received on the first port to be translated to the second serial protocol, and then transferred to the second port. A second translation circuit of the serial buffer allows packets received on the second port to be translated to the first serial protocol, and then transferred to the first port. Translations may be performed in response to information included in the headers of the received packets, including source ID values, destination ID values and/or case number values.

Protocol translation in a serial buffer

Within a serial buffer, request packets are written to available memory blocks of a memory buffer, which are identified by a free buffer pointer list. When a request packet is written to a memory block, the memory block is removed from the free buffer pointer list, and added to a used buffer pointer list. Memory blocks in the used buffer pointer list are read, thereby transmitting the associated request packets from the serial buffer. When a request packet is read from a memory block, the memory block is removed from the used buffer pointer list and added to a request buffer pointer list. If a corresponding response packet is received within a timeout period, the memory block is transferred from the request buffer pointer list to the free buffer pointer list. Otherwise, the memory block is transferred from the request buffer pointer list to the used buffer pointer list.

Serial buffer to support request packets with out of order response packets

A method and apparatus for adaptive buffer management for traffic optimization on switches have been disclosed where pattern injection and traffic monitoring with forced congestion allows optimizing buffers while accounting for actual system delays.

Method and apparatus for adaptive buffer management for traffic optimization on switches

A method and apparatus for selective packet discard have been disclosed where two bits are added to a packet to indicate various discard options.

Method and apparatus for selective packet discard

A multi-queue FIFO memory device that uses existing pins of the device to load a desired number of queues (N) into a queue number register is provided. The queue number register is coupled to a queue size look-up table (LUT), which provides a queue size value in response to the contents of the queue number register. The queue size value indicates the amount of memory (e.g., the number of memory blocks) to be included in each of the N queues. The queue size value is provided to a queue start/end address generator, which automatically generates the start and end address associated with each queue in response to the queue size value. These start and end addresses are stored in queue address register files, which enable proper memory read/write and flag counter operations.

Multi-queue address generator for start and end addresses in a multi-queue first-in first-out memory system

A serial buffer monitors an incoming stream of packets to identify single missing packets and multiple consecutive missing packets. Upon detecting multiple consecutive missing packets, an interrupt is generated, thereby stopping the data transfer. Upon detecting a single missing packet, a single missing packet identifier is inserted into the packet header of the packet that resulted in identification of the single missing packet. The incoming packets, including any inserted single missing packet identifiers, are written to a queue. When the water level reaches the water mark of the queue, the stored packets are read to create an outgoing packet stream. When a packet read from the queue includes an inserted single missing packet identifier, a dummy packet (e.g., a packet having a data payload of all zeros) is inserted into the outgoing packet stream. As a result, real-time applications are capable of processing the outgoing packet stream in a constant fashion.

Method to support lossless real time data sampling and processing on rapid I/O end-point

In accordance with the invention, time slot interchange switches ('TSIS') with bit error rate testing are described. The bit error rate testing includes creating a channel of data appropriate for bit error rate testing and monitoring the bit error rate testing on that channel.

Time slot interchange switch with bit error rate testing

On-chip resources of a serial buffer are accessed using priority packets of a Lite-weight protocol. A priority packet path is provided on the serial buffer to support priority packets. Normal data packets are processed on a normal data packet path, which operates in parallel with the priority packet path. The system resources of the serial buffer can be accessed in response to the priority packets, without blocking the flow of normal data packets. Thus, normal data packets may flow through the serial buffer with the maximum bandwidth supported by the serial interface. The Lite-weight protocol also supports read accesses to queues of the serial buffer (which reside on the normal data packet path). The Lite-weight protocol also supports doorbell commands for status/error reporting.

Growing community of inventors

Femont, CA, United States of America

Jason Z Mo