Intel Corporation

University Technology Corporation

University of Colorado

Jason W Klaus

Tahir Ghani

Mark T Bohr

Subhash M Joshi

Joseph M Steigerwald

Jack Hwang

Ryan Mackiewicz

Nadia M Rahhal-Orabi

Steven McClellan George

Willy Rachmady

Sean W King

Charles Henry Wallace

Ruth Amy Brain

Richard Daniel Noble

Mohit K Haran

John L Falconer

Hans Heinrich Funke

Reken Patel

James Jeong

Marvin Young Paik

Debashish Basu

Deepak S Rao

Seungdo An

Soley Ozer

Nadia M Rahhal-orabi

Nadia M Rahhai-Orabi

Kilhyun Bang

Daniel James Bahr

Andrew W Ott

Jack T Kavalieros

Ravi Pillarisetty

Niloy Mukherjee

Ofer Sneh

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Self-aligned contacts

An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

Via contact patterning method to increase edge placement error margin

A method of manufacturing a metal gate structure includes providing a substrate () having formed thereon a gate dielectric (), a work function metal () adjacent to the gate dielectric, and a gate metal () adjacent to the work function metal; selectively forming a sacrificial capping layer () centered over the gate metal; forming an electrically insulating layer () over the sacrificial capping layer such that the electrically insulating layer at least partially surrounds the sacrificial capping layer; selectively removing the sacrificial capping layer in order to form a trench () aligned to the gate metal in the electrically insulating layer; and filling the trench with an electrically insulating material in order to form an electrically insulating cap () centered on the gate metal.

Metal gate structure and method of manufacturing same

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Portland, OR, United States of America

Jason W Klaus