Intel Corporation

Tahoe Research, Ltd.

Jason W Brandt

Gilbert A Neiger

Vedvyas Shanbhogue

Ravi L Sahita

Baiju V Patel

Barry E Huntley

Richard A Uhlig

Robert T George

Beeman C Strong

Bret L Toll

Deepak K Gupta

Robert Valentine

Michael Mishaeli

Jonathan D Combs

Eliezer Weissmann

Joseph Nuzman

Robert S Chappell

Asit K Mallick

Anil Aggarwal

David M Durham

Mark Jay Charney

Michael Lemay

Efraim Rotem

Hong Wang

Stephen H Gunther

Prashant Sethi

Ahmad Yasin

Jesus Corbal

Alon Naveh

Milind Baburao Girkar

Gautham N Chinya

John Thomas Shen

Bryant E Bigbee

Shivnandan D Kaushik

Xiang Chris Zou

Richard A Hankins

Ofer Levy

Christopher J Hughes

Rajesh M Sankaran

Martin Guy Dixon

Uday R Savagaonkar

Matthew C Merten

James B Crossland

Xiaoning Li

Elmoustapha Ould-Ahmed-Vall

Krishnakanth Venkata Sistla

Avinash N Ananthakrishnan

Ankush Varma

Jeremy J Shrall

H Peter Anvin

Lihu Rappoport

Ian M Steiner

Edward Thomas Grochowski

Andrew V Anderson

Andrew J Herdrich

Srinivas Chennupaty

Inder M Sodhi

Stephen Anthony Fischer

David B Papworth

Ashok Raj

Sarathy Jayakumar

Steven L Grobman

Tsvika Kurts

Ashish V Choubal

Vinodh Gopal

Zeev Sperber

Michael E Kounavis

Raanan Sade

Steven M Bennett

Kun Tian

Karanvir S Grewal

Dheeraj R Subbareddy

Eugene Gorbatov

Venkateswara Rao Madduri

Erik C Cota-Robles

Utkarsh Y Kakaiya

Dion Rodgers

Philip R Lantz

David A Koufaty

Vadim Sukhomlinov

Huy Van Nguyen

Ganapati Srinivasa

Ronak Singhal

Stalinselvaraj Jeyasingh

Sergiu D Ghetie

Siddhartha Chhabra

Ren Wang

Andrew F Glew

Carlos V Rozas

Jr-Shian Tsai

Sanjay Kumar

Raghunandan Makaram

Per H Hammarlund

Scott Dion Rodgers

Ittai Anati

Wei Ey Li

Russell Jerome Fenger

Daniel Nemiroff

James Paul Held

Lawrence O Smith

A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width

Processors, methods, and systems for user-level interprocessor interrupts are described. In an embodiment, a processing system includes a memory and a processing core. The memory is to store an interrupt control data structure associated with a first application being executed by the processing system. The processing core includes an instruction decoder to decode a first instruction, invoked by a second application, to send an interprocessor interrupt to the first application; and, in response to the decoded instruction, is to determine that an identifier of the interprocessor interrupt matches a notification interrupt vector associated with the first application; set, in the interrupt control data structure, a pending interrupt flag corresponding to an identifier of the interprocessor interrupt; and invoke an interrupt handler for the interprocessor interrupt identified by the interrupt control data structure.

User-level interprocessor interrupts

Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.

Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacks

In one embodiment, a processor includes: a front end circuit to fetch and decode a read list instruction, the read list instruction to cause storage to a memory of a software-provided list of processor state information; and an execution circuit coupled to the front end circuit. The execution circuit, in response to the decoded read list instruction, is to read the processor state information stored in the processor and store each datum of the processor state information into an entry of a data table in the memory. Other embodiments are described and claimed.

System, apparatus and methods for performant read and write of processor state information responsive to list instructions

Technologies disclosed herein provide cryptographic computing with cryptographically encoded pointers in multi-tenant environments. An example method comprises executing, by a trusted runtime, first instructions to generate a first address key for a private memory region in the memory and generate a first cryptographically encoded pointer to the private memory region in the memory. Generating the first cryptographically encoded pointer includes storing first context information associated with the private memory region in first bits of the first cryptographically encoded pointer and performing a cryptographic algorithm on a slice of a first linear address of the private memory region based, at least in part, on the first address key and a first tweak, the first tweak including the first context information. The method further includes permitting a first tenant in the multi-tenant environment to access the first address key and the first cryptographically encoded pointer to the private memory region.

Cryptographic computing using encrypted base addresses and used in multi-tenant environments

System, method, and apparatus embodiments for creating, using, and managing protected cryptography keys are described. In an embodiment, an apparatus includes a decoder, an execution unit, and a cache. The decoder is to decode a single instruction into a decoded single instruction, the single instruction having a first source operand to specify encrypted data and a second source operand to specify a handle including a first including ciphertext of an encryption key, an integrity tag, and additional authentication data. The execution unit is to execute the decoded single instruction to perform a first check of the integrity tag against the ciphertext and the additional authentication data for any modification to the ciphertext or the additional authentication data, perform a second check of a current request against one or more restrictions specified by the additional authentication data of the handle, decrypt the ciphertext to generate an encryption key only when the first check indicates no modification to the ciphertext or the additional authentication data and the second check indicates the one or more restrictions are not violated, decrypt the encrypted data with the encryption key to generate unencrypted data, and provide the unencrypted data as a result of the single instruction. The cache is to store the handle, wherein only a portion of the integrity tag is to be used in a lookup of the handle.

Creating, using, and managing protected cryptography keys

Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.

Apparatuses and methods for speculative execution side channel mitigation

Systems, methods, and apparatuses relating to circuitry to implement an instruction to create and/or use data that is restricted in how it can be used are described. In one embodiment, a hardware processor comprises a decoder of a core to decode a single instruction into a decoded single instruction, the single instruction comprising a first input operand of a handle including a ciphertext of an encryption key (e.g., cryptographic key), an authentication tag, and additional authentication data, and a second input operand of data encrypted with the encryption key, and an execution unit of the core to execute the decoded single instruction to: perform a first check of the authentication tag against the ciphertext and the additional authentication data for any modification to the ciphertext or the additional authentication data, perform a second check of a current request of the core against one or more restrictions specified by the additional authentication data of the handle, decrypt the ciphertext to generate the encryption key only when the first check indicates no modification to the ciphertext or the additional authentication data, and the second check indicates the one or more restrictions are not violated, decrypt the data encrypted with the encryption key to generate unencrypted data, and provide the unencrypted data as a resultant of the single instruction.

Apparatuses, methods, and systems for instructions for usage restrictions cryptographically tied with data

Techniques and mechanisms for determining a latency event to be represented in performance monitoring information. In an embodiment, circuit blocks of a pipeline experience respective latency events at variously times during tasks by the pipeline which service a workload. The circuit blocks send to an evaluation circuit of the pipeline respective event signals which each indicate whether a respective latency event has been detected. The event signals are communicated in parallel with at least a portion of the pipeline. In response to a trigger event in the pipeline, the evaluation circuit selects an event signal, based on relative priorities of the event signals, which provides a sample indicating a detected latency event. Based on the selected event signal, a representation of the indicated latency event in provided to latency event count or other value performance monitoring information. In another embodiment, different time delays are applied to various event signals.

Device, system and method for identifying a source of latency in pipeline circuitry

A processor of an aspect includes a decode unit to decode an instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine that an attempted change due to the instruction, to a shadow stack pointer of a shadow stack, would cause the shadow stack pointer to exceed an allowed range. The execution unit is also to take an exception in response to determining that the attempted change to the shadow stack pointer would cause the shadow stack pointer to exceed the allowed range. Other processors, methods, systems, and instructions are disclosed.

Processors, methods, systems, and instructions to protect shadow stacks

A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.

Processor extensions to protect stacks during ring transitions

Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

Apparatuses and methods for a processor architecture

Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor core includes an instruction fetch circuit to fetch instructions; a branch target buffer comprising a plurality of entries that each include a thread identification (TID) and a privilege level bit; and a branch predictor, coupled to the instruction fetch circuit and the branch target buffer, to predict a target instruction corresponding to a branch instruction based on at least one entry of the plurality of entries in the branch target buffer, and cause the target instruction to be fetched by the instruction fetch circuit.

Microarchitectural mechanisms for the prevention of side-channel attacks using a thread identification (TID) and a privilege level bit

Embodiments for memory bandwidth monitoring extensible counters are described. In embodiments, an apparatus includes memory bandwidth monitoring hardware to monitor an event, a shared cache to be shared by multiple cores. At least one of the cores is to execute multiple threads and includes at least three registers. The first register is programmable by software to store a thread identifier of one of threads and an event identifier of the event during execution of the thread. At least one value of the event identifier corresponds to a shared cache miss. The second register is to provide to the software a second value corresponding to a number of bits available to represent the count. The third register is to provide to the software a count of occurrences of the event and an indicator to indicate whether the count reached a maximum count representable by the number of bits.

Memory bandwidth monitoring extensible counter

A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.

Methods, apparatus, and instructions for user-level thread suspension

Growing community of inventors

Austin, TX, United States of America

Jason W Brandt