Avago Technologies General IP (singapore) Pte. Ltd.

Agilent Technologies, Inc.

Avago Technologies General IP Pte, Ltd.

Jason Todd Gentry

David D Balhiser

Brady A Koenig

Richard S Rodgers

Gayvin E Stong

Brian C Miller

Richard Alan Krzyzkowski

William Scott Burton

Bryan Haskin

Jack D Benzel

Stephen Dixon

Ronald G Harber

M Jason Welch

Paul J Marcoux

An embodiment of a method for register placement in an integrated circuit (IC) includes determining a data path between circuit elements, placing at least one register along the data path, performing a static timing analysis on the data path, extracting top-level timing data to develop an extended timing path, the extended timing path comprising a plurality of timing path segments; processing the top-level timing data to determine whether the extended timing path violates a timing requirement, and moving the at least one register along the data path to satisfy the timing requirement if the timing requirement is violated.

System and method for automatic timing-based register placement and register location adjustment in an integrated circuit (IC)

A floor planning tool is provided that performs the functions that are typically performed by floor planning tools, but in addition, determines the supply of routing resources and the demand on routing resources for all routing channels while applying variable routing rules and static timing estimations to arrive at a preliminary routed floor plan. This drastically reduces the number of iterations that subsequently will need to be performed by the floor planning tool and by routing and static timing analysis tools to arrive at a final routed floor plan.

Computer system and method for performing a routing supply and demand analysis during the floor planning stage of an integrated circuit design process

A computer system performs a verification process that quickly and efficiently determines a temperature rise of DC conductor lines of an IC design caused by Joule heating in nearby AC conductor lines of the IC design, and whether the temperature rise is acceptable in terms of an electromigration performance of the IC design.

Computer system and method for determining a temperature rise in direct current (DC) lines caused by joule heating of nearby alternating current (AC) lines

Differences between block interfaces of a partitioned logic block in two floorplans of an integrated circuit can be determined by comparing an image of pins of a partitioned logic block in a first floorplan of the integrated circuit with an image of pins of the partitioned logic block in a second floorplan of the integrated circuit. The second floorplan can represent a new floorplan design resulting from a change to an integrated circuit design represented by the first floorplan. If no differences exist between pins of the partitioned logic block in the first and second floorplans, information representing the partitioned logic block in the second floorplan can be substituted with information representing the partitioned logic block in the first floorplan.

System and method for ensuring partitioned block physical compatibility between revisions of an integrated circuit design

The present invention is a method for collecting, analyzing, and displaying statistics regarding block pin placement prior to routing of an integrated circuit. The statistics are graphically displayed in a graphical user interface (GUI). The GUI graphically displays indications of where block pin congestion problems lie, which allows an integrated circuit designer to quickly pinpoint and correct pin placement in areas of pin congestion to alleviate congestion in these areas prior to routing.

Methods to gather and display pin congestion statistics using graphical user interface

Under control of an input signal, a signal line is driven toward a first voltage by coupling a first current path to the signal line. While the first current path is coupled to the signal line, 1) a charge boost is provided to the signal line to increase the rate at which a voltage on the signal line switches toward the first voltage, and 2) current flow through the signal line is clamped to prevent a voltage on the signal line from reaching the first voltage. The current flow may be clamped by means of a resistor in the first current path, and the charge boost may be provided by a capacitor that is coupled in parallel with the resistor.

Driver-side current clamping with non-persistent charge boost

In one disclosed method, a dynamic signal is driven onto a driven end of a first signal line, and an ungrounded bias signal is driven onto a driven end of a second signal line. The ungrounded bias signal is then received at a receiving end of the second signal line, and the dynamic signal is received at a receiving end of the first signal line. The receiving end of the second signal line is coupled to a first input of a quasi-differential receiver, and the receiving end of the first signal line is coupled to a second input of the receiver. The ungrounded bias signal is used to bias a toggle point of the receiver, and the dynamic signal is used to toggle an output of the receiver. Variations of this method, and apparatus that can perform this and other methods, are also disclosed.

Propagation of a dynamic signal to a quasi-differential receiver biased by an ungrounded driver-side bias signal

A method and system of identifying one or more nets in a digital IC design that are at risk of electromigration comprises selecting a manufacturing process for the digital IC design and obtaining a clock period and process voltage. A voltage waveform transition time and effective capacitance is calculated for one or more of the nets. A maximum allowable effective capacitance for each one of the nets is calculated based upon a peak current analysis or an RMS current analysis. The effective capacitance for each net is compared against the maximum allowable capacitance to identify those nets that are at risk of failure due to the effects of electromigration.

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Wellington, CO, United States of America

Jason Todd Gentry