Marvell International Limited

Marvellworld Trade Ltd.

Applied Micro Circuits Corporation

Jason T Su

Sehat Sutardja

Hong-Yi Chen

Jensen Tjeng

Jason Sheu

Karthik Swaminathan

Winston Lee

Jitendra Khare

Yuntian Chen

Bin Liang

Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation.

Method and apparatus for timing closure

A device (e.g., an integrated circuit memory device such as a static random access memory device) includes word line drivers. Each of the word line drivers includes a pull-up device that is coupled to a node via a shared line. A precharge device is coupled between a power supply and the node. The precharge device and a pull-up device for a selected word line driver are controlled to allow the power supply to charge the node and then to allow the charge stored in the node to flow into a word line corresponding to the selected word line driver.

Integrated circuit memory device with read-disturb control

Providing for improved write processes of a semiconductor memory are disclosed herein. By way of example, a programmable write assist can be provided that includes partially discharging a supply voltage applied to a memory cell. Partially discharging the supply voltage can improve write speeds to the memory cell, as well as improve reliability of the write process. A write assist circuit can cause the discharging in response to a resistance-modulated signal. Moreover, the resistance-modulated signal can be configured to control an amount or speed of the discharging of the supply voltage. Further, modulation control can be provided to mitigate discharging of the supply voltage beyond a target level, to reduce data loss in a target data cell or an adjacent data cell.

Programmable resistance-modulated write assist for a memory device

Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by a power supply voltage generator circuit, the generated power supply voltage being substantially equal to or less than a global power supply voltage provided to one or more transistors of the SRAM cell during a write-enable or power-down mode.

Method and apparatus for supplying power to a static random access memory (SRAM) cell

A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array.

Processor with memory delayed bit line precharging

A flip-flop circuit includes a charge injection module, a sense amp module, and a latch module. The charge injection module is configured to, in response to a clock signal, selectively provide electrical charge from a power supply to a first node. The sense amp module is configured to adjust a voltage of a second node in response to detecting a voltage of the first node crossing a threshold while the charge injection module is providing the electrical charge to the first node. The latch module is configured to in response to the clock signal, store a value based on a voltage of the second node. The latch module is also configured to provide the value as an output of the flip-flop circuit.

Charge-injection sense-amp logic

Write-assist and power-down circuit for low power SRAM applications

A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to access second instructions stored in the first word line or a second word line. The precharge circuit (i) precharges first bit lines connected to the first word line prior to accessing each of the first and second instructions. The control module adjusts a rate of a clock signal from a first rate to a second rate. The amplifier module accesses the first instructions based on (i) the first word line signal and (ii) the clock signal at the first rate, and accesses the second instructions based on (i) the second word line signal and (ii) the clock signal at the second rate.

Processor instruction cache with dual-read modes

An address decoder that includes a plurality of predecoders configured to (i) receive and logically combine a clock signal and address signals and (ii) generate addresses and complementary addresses. At least one of the plurality of precoders includes a first logic gate configured to receive the clock signal and one of the address signals, and a second logic gate configured to receive the clock signal and an output of the first logic gate. The address decoder further includes a decoder configured to generate a decoder output based on the addresses and complementary addresses.

Address decoder

An Asymmetric Sense-Amp Flip-Flop (ASAFF) is disclosed that may achieve zero setup time and short clock-to-Q delays. The ASAFF captures input data at a clock transition by setting values of a first node and a second node in a manner that is input data value dependent. If the input data is at the first input data value, the first node is set and held at a first storage value after a first delay, and the second node is set and held at a second storage value after a second delay, and if the input data is at a second input data value, the first node is set and held at a third storage value after a third delay, and the second node is set and held at a fourth storage value, after a fourth delay. This internal-path dependent difference in delay enables ASAFF to achieve zero setup time.

Aysmmetric sense-amp flip-flop

A processor including a memory and a control module. The memory has an array of cells. The control module is configured to: determine a number of access cycles along a first word line; determine an extended period based on the number of the access cycles; generate a word line signal to maintain the first word line in an activated state during (i) an initial period and (ii) the extended period; and access a first cell during the extended period. The first cell is connected to the first word line. The control module is further configured to deactivate the word line and maintain the first word line in a deactivated state while accessing a second cell connected to the first word line. The accessing of the second cell is based on a bit line separation provided during the extended period.

A processor includes a cache memory that has an array, word lines, and bit lines. A control module accesses cells of the array during access cycles to access instructions stored in the cache memory. The control module performs one of a first discrete read and a first sequential read to access instructions in a first set of cells of the array that are connected to a first word line and selectively performs one of a second discrete read and a second sequential read based on a branch instruction to access instructions in a second set of cells of the array that are connected to a second word line. The second word line is different than the first word line.

A clock gater includes a first circuit configured to receive a clock signal. The first circuit includes a first subcircuit and a second subcircuit. A latch is configured to receive the clock signal. The latch is connected to the first circuit at each of a first node and a second node. The latch includes a third subcircuit and a fourth subcircuit. The first subcircuit and the third subcircuit are configured to pull the first node and the second node, respectively, to a common precharge voltage in response to a first state of the clock signal in order to pass the clock signal. The second subcircuit and the fourth subcircuit are configured to pull the first node and the second node, respectively, to complementary voltages in response to a second state of the clock signal in order to pass the clock signal, the second state of the clock signal being different from the first state of the clock signal.

Clock gater system

A circuit receives an input signal characterized by a first pair of rail voltages and generates in response thereto an output signal characterized by a second pair of rail voltages. The circuit comprises first and second transistors coupled in series between a high reference voltage and a low reference voltage. The input signal drives a control lead of the second transistor. The logical inverse of the input signal drives a control lead of a third transistor, which couples a charge source to the control lead of the first transistor in response thereto in order to turn off the first transistor. The charge source can be either a voltage source or a charged capacitive node. Of importance, the third transistor does not have to overcome contention with other transistors to turn off said first transistor.

Growing community of inventors

Los Altos, CA, United States of America

Jason T Su