Adeia Semiconductor Bonding Technologies Inc.

Jason Sweis

Gary W Grube

Igor Y Khandros

Thomas H DiStefano

Gaetan L Mathieu

David A Gibson

Laurie Union

John A Grange

Kenneth Burton Gilleo

Gaetan Mathiew

A semiconductor chip mounting component includes a support structure adapted to engage a semiconductor chip. The support structure has a top surface, a bottom surface, and a gap extending through the support structure for defining first and second portions of the support structure on opposite sides of the gap. The support structure includes at least one elongated bus disposed alongside the gap, on the second portion of the support structure. The support structure includes a plurality of electrically conductive leads, each lead having a connection section extending across the gap, the connection section having a first end disposed on the first portion of the support structure, and a second end secured to the bus. Each lead includes a frangible section disposed between the first and second ends of the connection section, the frangible section having a cross-sectional area that is smaller than a cross-sectional area of the connection section. The gap is open at the bottom surface of the support structure. A semiconductor chip is disposed beneath the bottom surface of the support structure. The leads are adapted to be bonded to contacts on the semiconductor chip by breaking the frangible sections of the leads so as to disconnect the second ends of the leads from the bus and engage the leads with the contacts of the semiconductor chip.

Connection components with frangible leads and bus

A connection component for electrically connecting a semiconductor chip to a support substrate incorporates a preferably dielectric supporting structure defining gaps. Leads extend across these gaps so that the leads are supported on both sides of the gap. The leads therefore can be positioned approximately in registration to contacts on the chip by aligning the connection component with the chip. Each lead is arranged so that one end can be displaced relative to the supporting structure when a downward force is applied to the lead. This allows the leads to be connected to the contacts on the chip by engaging each lead with a tool and forcing the lead downwardly against the contact. Preferably, each lead incorporates a frangible section adjacent one side of the gap connecting one end of the lead connection section to a bus extending alongside the gap. The frangible section is broken when the lead is engaged with the contact.

Method of making connections to a semiconductor chip assembly

A method for creating an interface between a chip and chip carrier includes spacing the chip a given distance above the chip carrier, and then introducing a liquid in the gap between the chip and carrier. Preferably, the liquid is an elastomer which is hardened into a resilient layer after its introduction into the gap. In another preferred embodiment, the terminals on a chip carrier are planarized or otherwise vertically positioned by deforming the terminals into set vertical locations with a plate, and then hardening a liquid between the chip carrier and chip.

Method of forming interface between die and chip carrier

In a semiconductor inner lead bonding process, a connection component having leads is disposed on the chip surface so that the leads lie above the contacts. A bond region of each lead is forced downwardly by a tool into engagement with a contact on the chip while a first or proximal end of the lead remains attached to a dielectric support structure. The lead is deformed into an S-shaped configuration by moving the bonding tool horizontally towards the proximal or first end of the lead, thereby forcing the bonding region towards the first end and bending or buckling the lead. Alternatively, the lead is bent downwardly by a tool and the tool may then be disengaged from the lead, shifted away from the proximal end of the lead and again advanced downwardly to secure the lead to the chip contact.

Shaped lead structure and method

A bonding tool for bonding inner leads to semiconductor chips is arranged to capture and align elongated lead sections extending in any one of plural directions, and preferably, in any one of two mutually orthogonal directions. Thus, the tool can be applied to align and bond all of the leads to a chip without turning the tool or the chip even where the leads extend in multiple directions.

Growing community of inventors

Sunnyvale, CA, United States of America

Jason Sweis