Hpl Technologies, Inc.

Silicon Aquarius, Inc.

Jason Stevens

Daran DeShazo

Agustinus Sutandi

Craig Michael Waller

Wayland Bart Holland

Craig Waller

Gary Johnson

A low standby current power-on reset circuit is described. A first NMOS transistor's drain is coupled to a first PMOS transistor's drain; source coupled to ground line; and gate coupled to a first capacitor coupled to ground line. The first PMOS transistor's source is coupled to power line; gate coupled to second capacitor coupled to ground line; and drain provides a power-on reset indication. A second PMOS transistor's source is coupled to power line; drain is coupled to drain of second NMOS transistor, gates of first PMOS, second PMOS, and second NMOS transistors, and second capacitor. The second NMOS transistor's source is coupled to gate of first NMOS transistor and first capacitor. A discharge circuit is coupled to power line, ground line, and first and second capacitors for discharging the capacitors when a voltage on power line drops below a level determined by the second PMOS transistor's threshold voltage.

Low standby current power-on reset circuit

An OTP bit cell includes a latch circuit of cross-coupled inverters. A floating gate PMOS transistor is inserted in each of the inverters. One or the other of the floating gate PMOS transistors is programmed through an included programming circuit so that a differential output of the latch circuit provides a corresponding logic state that is the same each time when read. To program a selected floating gate PMOS transistor, appropriate write inputs are applied to the programming circuit while a high reference voltage to the OTP bit cell is raised to a level such that the selected floating gate PMOS transistor is programmed.

One-time-programmable bit cell with latch circuit having selectively programmable floating gate transistors

A dynamic random access memory,includes an array,of physical rows and columns of memory cells, the cells of each row coupled to first and second wordlines,and first and second bitlines,A direct input/output data path,having a width equal to a width of the rows supports simultaneous writing to each of the cells along a selected row using the first wordlines and first bitlines during a single access cycle without restore.

Dynamic random access memory with write-without-restore and systems and methods using the same

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Plano, TX, United States of America

Jason Stevens