Intel Corporation

Jason Steill

Zhiguo Qian

Brandon C Marin

Leonel R Arana

Jeremy D Ecton

Tarek A Ibrahim

Suddhasattwa Nad

Dingying David Xu

Sri Chaitra Jyotsna Chavali

Hongxia Feng

Marcel Arlan Wall

Jieying Kong

Bohan Shan

Sarah Blythe

Yiyang Zhou

An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

Selectively roughened copper architectures for low insertion loss conductive features

Growing community of inventors

Phoenix, AZ, United States of America

Jason Steill