Intel Corporation

Jason Sandri

Monib Ahmed

Tina C Zhong

Kenneth P Griesser

Lori R Borger

Ian S Walker

Sergiu D Ghetie

Neeraj S Upasani

David P Turley

Zhangping Chen

Sanu K Mathew

Jesse R Walker

Mark A Anders

Steven J Tu

Himanshu Kaul

Adrian R Pearson

Peter Munguia

Charles A Peterson

Steve J Brown

Pat Brouillette

Sean T Baartmans

Matthew B Pedersen

Horaira Abu

Michael J Wiznerowicz

Ruben Ramirez

Orlando Davila

Brian Harris

Embodiments may be generally directed to techniques to encrypt and decrypt data in a first fuse block array using an encryption key of a second fuse block array, the second fuse block array having the encryption key comprising a plurality of segments of bits, an inverse encryption key comprising a second plurality of segments of bits, each segment of the inverse encryption key to correspond with a particular segment of the encryption key, and a random pattern having equally distributed bit values, the random pattern to enable detection of voltage attacks on the second fuse block array.

Techniques to protect fuses against non-destructive attacks

An instruction and logic for a Simon-based hashing for validation are described. In one embodiment, a processor comprises: a memory the memory to store a plurality of values; and a hash circuit comprising a Simon cipher circuit operable to receive the plurality of values from the memory, to apply a Simon cipher, and to generate an output for each of the plurality of values; and circuitry coupled to the Simon cipher circuit to combine outputs from the Simon cipher circuit for each value of the plurality of values into a hash digest that is indicative of whether the values in the memory are valid.

Simon-based hashing for fuse validation

In accordance with some embodiments, the way in which the fuses are sensed and, particularly, their order may be made more random so that it is much more difficult to simply exercise the device and determine all the values of the storage elements within the fuse array. One result is a more secure storage device.

Random fuse sensing

In accordance with some embodiments, fuse information may be written into a fuse array in a way that provides sufficient redundancy, making it harder for malicious parties to attack the fuse array.

Redundant fuse coding

In accordance with some embodiments, multiple blind debug passwords are provided. Each of a plurality of interested entities may have its own password and each password may unlock a specific set of features offered by an integrated circuit. In some embodiments each entity does not know the other passwords of the other entities. Potentially interested entities include an integrated circuit end customer, the original equipment manufacturer, the entity that provided the features to the integrated circuit and a conditional access provider. All debug features may be controlled solely via access to the debug tiers which are accessed by multiple debug passwords. Lower tier passwords are required in order to access higher tiers. Debug features may be separated into multiple tiers with more intrusive access requiring multiple debug passwords in order to gain access.

Tiered access to on chip features

In accordance with some embodiments, instead of providing replacement rows, an area within a fuse array may be reserved for storing addresses of bits that are defective. Then these bits can be readily repaired by simply reading the stored state of identified defective bit, and inverting the stored state of the identified defective bit to get the correct output.

Bit based fuse repair

In one embodiment described herein, on-die programmable fuses may be used. On-die programmable fuses may be programmed by entities other than the chip manufacturer after the fuse array chip has been manufactured and shipped out. However, other non-volatile memories may also be used.

On-die programmable fuses

In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

On-die logic analyzer for semiconductor die

In one embodiment, the present invention is directed to a logic analyzer such as may be implemented on a system-on-chip or another semiconductor device. The analyzer can include multiple lanes each having a filter to receive and filter debug data, a compressor to compress the debug data passed by the filter, a buffer, and a controller to store the compressed debug data into the buffer, where the compressed debug data can be stored without timing information. Other embodiments are described and claimed.

Providing an on-die logic analyzer (ODLA) having reduced communications

An integrated circuit (IC) die includes a plurality of edge counters. Each edge counter is provided to detect at least one change in signal level at a respective location on the IC die. The IC die is in communication with a memory and also includes an event recording circuit on the IC die provided to store states of the counters in the memory.

On-chip storage of hardware events for debugging

The disclosure relates to a control mechanism for controlling access by multiple logical processors to shared resources on a common microchip. The processors attempt to reserve exclusive use of needed resources by updating a resource descriptor. The resource descriptor describes which logical processors have exclusive use of which resources. In order to update the resource descriptor, a logical processor must first obtain exclusive access to the resource descriptor by updating a semaphore.

Growing community of inventors

Gilbert, AZ, United States of America

Jason Sandri