Ast Research, Inc.

Trw Limited

Jason S Kim

Charles F Raasch

James M Anderson

A method and apparatus using a virtual addressing buffer circuit afford address mapping and control flexibility to provide a unique opportunity for device emulation and software debugging. The method permits the emulation of a device which is physically not present in a CPU controlled system utilizing a virtual addressing buffer circuit. The method includes the step of storing a match address which corresponds to an address location of the device. The virtual addressing buffer intercepts an address request from a CPU for the address location of the device. Bits of the requested address which are not relevant to a determination of whether the requested address matches the match address are filtered out to produce a filtered request address. The filtered request address is compared with the match address, and a match indicator is activated when the filtered requested address matches the match address. A terminate command is provided to a bus controller connected to the CPU and a local memory when the match indicator is active. An interrupt sent to the CPU from the bus controller in response to the terminate command interrupts the CPU. An interrupt routine triggered by the CPU interruption copies emulated data stored in local memory to a memory status buffer. Upon completion of the interrupt routine, a second virtual addressing buffer circuit copies the emulated data stored in the local memory status buffer to the CPU so that it appears that the emulated device responded.

System and method utilizing a virtual addressing buffer circuit to

A virtual addressing buffer circuit has improved address mapping and control flexibility for improved physical resource management and a unique opportunity for forward-compatible system design. The virtual addressing buffer formats the output address utilizing a format register as a combination of the new address bits and the original input address bits. The ability to format the output address enables the user to replace certain address bits without requiring that the entire address be replaced. The virtual addressing buffer controls the output of several command signals to external circuits to indicate how the system should respond to the address output from the virtual addressing buffer. The command signals are controlled by a command register and are output from the virtual addressing buffer only when an address match has been verified. The virtual addressing buffer circuit filters out certain bits of an input address as indicated by a filter register before it verifies that the input address matches a stored address. The bit pattern in the filtering register is not fixed, so any bit location in the input address can be filtered out before the address is verified. Once an address match has been detected, the virtual addressing buffer circuit replaces the entire input address with a new formatted address.

Physical memory optimization using programmable virtual address buffer

A memory mapped keyboard controller within a peripheral controller for use in an Industry Standard Architecture (ISA) computer provides a method and apparatus for efficiently monitoring and reading a keyboard switch matrix. In a first mode of operation, the controller activates all the columns and monitors all the rows in the switch matrix to detect when any one or more of the rows becomes active, indicating that at least one key on the keyboard has been pressed. When any row in the matrix is detected as active, then the keyboard controller enters a second mode wherein it selectively activates individual columns and monitors the rows in the switch matrix to detect which row and column contain the activated switch. When the switch location is determined, this location is interpreted by the keyboard controller into a scan code for the ISA computer.

Memory mapped keyboard controller

Virtual addressing buffer circuit

A method and apparatus for downloading instructions and other information to a peripheral controller for use in an Industry Standard Architecture (ISA) compatible computer provides a system which downloads instructions from the ISA compatible computer to an random access memory (RAM) accessible by the peripheral controller. The peripheral controller then executes these instructions to emulate the functions of conventional INTEL 8042 and 8742 series integrated circuits. The peripheral controller also provides other features not provided by the conventional 8042 or 8742 by executing other downloaded instructions located in the RAM.

Method and apparatus for down-loading instructions from a host computer

A current limiting circuit and technique is provided for preventing excessive current supplied to a circuit and for providing self-recovery characteristics thereto. The current limiting circuit includes an input for receiving a supply voltage for supplying power to the monitored circuit and an output for providing the power to the desired circuit being monitored. The circuit employs a drive transistor having a source connected to the input and a drain connected to the output. The drive transistor further includes a gate for receiving a control signal. A current mirror circuit is provided for sensing a current overload and adjusting the control signal to indicate the amount of current drawn. During normal current draw, the circuit provides the supply voltage as the output. When excessive current draw is detected, the drive transistor is turned off and the output current is thereby cut off. When the current decreases to normal current loads, the drive transistor is turned back on. In addition, a reset signal may be further generated when excessive current is detected to reset the internal logic on a chip, so as to correct the problem causing the excessive current draw. Furthermore, the monitored circuit and herein described current limiting circuit may be fabricated together on the same die or chip.

On chip current limiter

Method and apparatus for providing down-loaded instructions for

An interrupt driven peripheral controller for use in an Industry Standard Architecture (ISA) compatible computer provides a system to minimize power consumption as compared to conventional peripheral controllers. The peripheral controller utilizes an internal interrupt controller which responds to inputs from an ISA compatible microprocessor host, a keyboard, a mouse, and other devices connected to the I/O ports of the ISA compatible computer. The interrupt controller provides an interrupt register for the peripheral controller and generates an interrupt any time one or more of the devices controlled by the peripheral controller is activated. The peripheral controller enters a low power consumption mode if no interrupts are detected for a predetermined period of time. When the interrupt controller generates an interrupt, the peripheral controller is activated from it low power mode and services the device or devices which have caused the interrupt.

Internal interrupt controller for a peripheral controller

An electronic keyboard template for use with software applications programs is responsive to command signals transmitted by designated function keys on a computer keyboard. The template includes an LCD display screen for displaying icons representative of operations performed by the function keys, control circuitry, and driving circuitry for generating the display of the icons on the LCD screen. In a preferred embodiment, the control circuitry includes a microprocesor, a Random-Access-Memory, and a digital Look-Up-Table, and the driving circuitry comprises a matrix driver and a refresh sequencer. The driving circuitry may further include a DC-to-DC convertor, and a plurality of shift registers for energizing pixel locations designated within a grid system on the LCD screen. In an alternative embodiment, the control circuitry may be external to the template (e.g., within the keyboard).

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Los Angeles, CA, United States of America

Jason S Kim