Tabula, Inc.

Google Inc.

Imagination Technologies Limited

Apple Inc.

Stmicroelectronics N.v.

Altera Corporation

Other

Caustic Graphics, Inc.

Vitesse Semiconductor Corporation

Celestial Ai Inc.

Stmicroelectronics Gmbh

Jason Rupert Redgrave

Herman Henry Schmit

Albert Meixner

Steven L Teig

Ofer Shacham

Daniel Finchelstein

Brad Hutchings

Qiuling Zhu

Steven John Clohset

Luke Tilman Peterson

William R Mark

David Patterson

Martin L Voogel

Teju Khubchandani

Andrew Edward Caldwell

James Alexander McCombe

Neeti Desai

Trevis Chandler

Jerome Francis Duluk, Jr

Richard E Hessel

Sushma Shrikant Trivedi

Emerson S Fang

Steven R Norsworthy

Stephen L Dodgen

Hengwei Hsu

Donald C Stark

Joseph P Bratt

Vaughn Todd Arnold

Jack Benkual

Sidong Li

Matthew N Papakipos

Sam Ng

Nathan D Tuck

George Cuan

Zhaoyu Gong

Andre Rohe

Thomas Y Ho

Artem Vasilyev

Randy Renfu Huang

Edward Y Chang

Benjamin K Dodge

Dai Huang

Xiaoyu Ma

Tuan Anh Nguyen

Abbas Rashid

Hyunchul Park

Shun Wai Go

Abraham Mammen

Bo Hong

Joseph P Grass

Lindy Fung

Dilan Manatunga

Albert Suan-Wei Tsay

Andrew Tham

Joe Entjer

Manu Gulati

Daniel J Pugh

Timothy James Knight

Shahriar Rabii

Keith Robert Pflederer

Allan Douglas Knies

David S Warren

Vinod Chamarty

Don Stark

Hongil Yoon

Rahul Jagdish Thakur

Ji Kim

Asif Khan

Vikas Chandra

Fabrizio Basso

Aubrey Arthur Grey

Masumi Reynders

Michelle Tomasko

Weiping Liao

Stephen C Purcell

Philip Winterbottom

Martinus Bos

Daniel Gitlin

Tom Kronmiller

Joseph M Richards

James A Mccombe

Marc A Miller

Christopher Philip Alan Tann

Danny Thom

Edward T Chang

Timothy Horel

Thomas Y Yo

Cüneyt Özdaş

Teju Khubehandani

Cüneyt Özdaç

Matt Crowley

Daniel Frederic Finchelstein

Daniel Fredric Finchelstein

Various embodiments provide for clock signal distribution within a processor, such as a machine learning (ML) processor, using a photonic fabric.

Clock signal distribution using photonic fabric

In some aspects, systems and methods provide for forming groupings of a plurality of independently-specified computation workloads, such as graphics processing workloads, and in a specific example, ray tracing workloads. The workloads include a scheduling key, which is one basis on which the groupings can be formed. Workloads grouped together can all execute from the same source of instructions, on one or more different private data elements. Such workloads can recursively instantiate other workloads that reference the same private data elements. In some examples, the scheduling key can be used to identify a data element to be used by all the workloads of a grouping. Memory conflicts to private data elements are handled through scheduling of non-conflicted workloads or specific instructions and/or deferring conflicted workloads instead of locking memory locations.

Graphics processor with non-blocking concurrent architecture

Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.

Multistage collector for outputs in multiprocessor systems

A method is described that includes executing a convolutional neural network layer on an image processor having an array of execution lanes and a two-dimensional shift register. The two-dimensional shift register provides local respective register space for the execution lanes. The executing of the convolutional neural network includes loading a plane of image data of a three-dimensional block of image data into the two-dimensional shift register. The executing of the convolutional neural network also includes performing a two-dimensional convolution of the plane of image data with an array of coefficient values by sequentially: concurrently multiplying within the execution lanes respective pixel and coefficient values to produce an array of partial products; concurrently summing within the execution lanes the partial products with respective accumulations of partial products being kept within the two dimensional register for different stencils within the image data; and, effecting alignment of values for the two-dimensional convolution within the execution lanes by shifting content within the two-dimensional shift register array.

Convolutional neural network on programmable two dimensional image processor

In an aspect, an update unit can evaluate condition(s) in an update request and update one or more memory locations based on the condition evaluation. The update unit can operate atomically to determine whether to effect the update and to make the update. Updates can include one or more of incrementing and swapping values. An update request may specify one of a pre-determined set of update types. Some update types may be conditional and others unconditional. The update unit can be coupled to receive update requests from a plurality of computation units. The computation units may not have privileges to directly generate write requests to be effected on at least some of the locations in memory. The computation units can be fixed function circuitry operating on inputs received from programmable computation elements. The update unit may include a buffer to hold received update requests.

Atomic memory update unit and methods

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating, by an image sensor of a computing device, frame data comprising sub-frames of image pixel data. A first resource of the system-on-chip provides the frame data to a second resource of the system-on-chip. The frame data is provided to the second resource using a first data path included in the system-on-chip. The first resource provides a token to the second resource using a second data path included in the system-on-chip. A processor of the system-on-chip, uses the token to synchronize production of sub-frames of image pixel data provided by the first resource to the second resource and to synchronize consumption of the sub-frames of image pixel data received by the second resource from the elastic memory buffer.

Synchronized data chaining using on-chip cache

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.

Way partitioning for a system-level cache

An image processor unit is described. The image processor unit includes a plurality of inputs to receive at least one input image. The image processor unit includes a plurality of outputs to provide at least one output image. The image processor unit includes a network coupled to the plurality of inputs and the plurality of outputs. The network is to couple at least one of the inputs to at least one of the outputs. The image processor unit includes an image processor circuit coupled to the network. The network to route an input image that is received at one of the inputs to the image processor circuit. The image processor circuit is to execute image signal processing program code to generate a processed output image from the input image. The network is to route the processed output image to at least one of the outputs.

Configurable and programmable image processor unit

A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.

Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register

An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.

Line buffer unit for image processor

Growing community of inventors

Mountain View, CA, United States of America

Jason Rupert Redgrave