Advanced Micro Devices Corporation

Ati Technologies Ulc

Jason Phillip Cain

Bhanwar Singh

Iraj Emami

Carsten Hartig

Chris Haidinyak

Omid Rowhani

Ioan Cordos

Harish Kumar Bolla

Hoang Q Dao

Michael Davinson Sherriff

Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

Metal track cutting in standard cell layouts

The claimed subject matter provides a system and/or a method that facilitates utilizing a resolution enhancement for a circuit feature. A scanning electron microscope component () can provide at least one two-dimensional image of the circuit feature. An image analysis engine () can analyze the two-dimensional image. An advanced process control (APC) engine () can generate at least one instruction for at least one of a feed forward control and a feedback control and a process component () can utilize the at least one instruction to minimize an error.

Advanced process control framework using two-dimensional image analysis

A method includes collecting optical data from an unpatterned region including a first process layer. At least one optical parameter of the first process layer is determined based on the optical data associated with the unpatterned region. Optical data is collected from a patterned region including a second process layer. At least one characteristic of the patterned region is determined based on the optical data associated with the patterned region and the at least one optical parameter.

Incorporating film optical property measurements into scatterometry metrology

The disclosed embodiments reduce across-chip performance variation through non-contact electrical metrology. According to a feature is a process control system that includes a component that measures transistor electrical performance in a product wafer. Also included in the system is a mapping component that converts the transistor performance into exposure dose values and a process tool that communicates the exposure dose value to a scanner. The exposure dose value is fed back for optimization of future chip exposures. The disclosed embodiments directly optimize transistor performance, thus controlling an important parameter in many integrated circuits.

Scanner optimization for reduced across-chip performance variation through non-contact electrical metrology

The claimed subject matter can provide a mechanism for ascertaining a variety of metrological data relating to one or more features (e.g., a transistor gate) of a chip/wafer. In addition, results of electrical testing on the chip/wafer can also be gathered and, together with the metrological data, input to a data store. From the information in the data store, a three-dimensional model for the feature(s) of the chip/wafer can be constructed and subjected to analysis, testing, and/or simulation. As well, the three-dimensional model can be optimized and an optimized three-dimensional model can be employed to affect process control in a feedback/forward manner, e.g., to apply optimizations to the next or the current wafer, respectively. Accordingly, the disclosed mechanisms may be used to optimize semiconductor performance, yield, or for research and development. In addition the three-dimensional model may be used in analysis, simulation, or debugging software.

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Sunnyvale, CA, United States of America

Jason Phillip Cain