Advanced Micro Devices Corporation

Jason Mulig

Arnold Y Louie

Michael R Bruce

Rosalinda M Ring

Victoria Jean Bruce

David Harry Eppes

Sean Michael O'Mullan

Paiboon Tangyunyong

Richard Jacob Wilcox

Charles F Hawkins

Edward I Cole, Jr

A method and apparatus for replacing a boot ROM and programmable fuses using a non-volatile memory and an interposer is disclosed. In one embodiment, an apparatus includes an integrated circuit (IC) implementing one or more processor cores. The apparatus further includes a non-volatile memory configured to store configuration settings and boot code for the IC. The apparatus further includes an interposer. Both of the IC and the non-volatile memory are mounted on a substrate of the interposer. The IC and the non-volatile memory are electrically coupled to one another through the substrate. During a system boot, the IC may access boot code and configuration settings from the non-volatile memory via electrical connections in the substrate that are externally inaccessible.

Integrated circuit boot code and fuse storage implemented on interposer-mounted non-volatile memory

A test circuit for exposing higher order speed paths. A test circuit includes a clock generation circuit coupled to a test clock control unit. The clock generation circuit is configured to receive an input clock signal and to generate an output clock signal. The test clock control unit is configured to selectively provide a user programmable test vector or a fixed test vector to control the generation of the output clock signal by the clock generation circuit depending upon a state of a first mode select signal.

Test circuit for exposing higher order speed paths

A method and apparatus mechanism for testing data processing devices are implemented. The test mechanism isolates critical paths by correlating a scanning microscope image with a selected speed path failure. A trigger signal having a preselected value is generated at the start of each pattern vector. The sweep of the scanning microscope is controlled by a computer, which also receives and processes the image signals returned from the microscope. The value of the trigger signal is correlated with a set of pattern lines being driven on the DUT. The trigger is either asserted or negated depending the detection of a pattern line failure and the particular line that failed. In response to the detection of the particular speed path failure being characterized, and the trigger signal, the control computer overlays a mask on the image of the device under test (DUT). The overlaid image provides a visual correlation of the failure with the structural elements of the DUT at the level of resolution of the microscope itself.

Data processing device test apparatus and method therefor

Growing community of inventors

Austin, TX, United States of America

Jason Mulig