Microsoft Technology Licensing, LLC

Other

Jason Matthew Gould

Ivan Nevraev

Mark Stefan Grossman

Martin J I Fuller

J Andrew Goossen

Juan Carlos Arevalo Baeza

Alexander Nankervis

Charles Neill Boyd

Michael Burrows

Zsolt Mathe

Jeffrey B Kay

Casey Leon Meekhof

Ketan K Dalal

David Floyd Aronson

Michael E Pietraszak

Matthew William Lee

Cole Brooking

James Andrew Goossen

David Ruzyski

Jack Elliott

John H Palevich

Andrew Dadi

Parham Mohadjer

Matthew Russell Kimball

Robert Charles Aldinger

Adam James Miles

Aaron Rodriguez Hernandez

Karen Elaine Stevens

Veena K Malwankar

Anna C Gould

Andrew Goossen

Nihar Mohapatra

Parikshit Gopal Narkhede

Adam J Miles

Methods and devices for managing first-in first-out (FIFO) queues in graphics processing are described. A dispatcher thread can receive a value of a write done pointer indicating a next memory location following one or more memory locations to which data has been written by a write thread of a graphics processing unit (GPU). The dispatcher thread can accordingly launch, based at least in part on the value of the write done pointer, multiple read threads on the GPU to read, in parallel and based on the write done pointer, the data from the FIFO queue.

FIFO queue, memory resource, and task management for graphics processing

Methods and devices for index buffer block compression in a computer system include a compressor in communication with a graphical processing unit (GPU). The methods and devices include selecting one or more primitives of at least a portion of a mesh formed by a total number of primitives for inclusion within a compressed index buffer block, the one or more primitives each associated with a number of indices each corresponding to a vertex within the mesh. The methods and devices may identify at least one redundant index in the number of indices associated with the one or more primitives of the compressed index buffer block. The methods and devices removing the at least one redundant index from the number of indices associated with the one or more primitives of the compressed index buffer block to form the compressed index buffer block as a set of one or more unique indices.

Index buffer block compression

Enhanced data buffer control in data systems is presented herein. In one example, a method includes establishing a pool of available memory pages tracked by memory pointers for use in a data structure, and processing requests for storing data to identify ones of the requests indicating data sizes that exceed a capacity of current pages included in the data structure. The method includes providing first pointers indicating start locations in the data structure to begin writing associated data, count information indicating quantities of the associated data able to be written in the current pages, and second pointers indicating at least one additional page in the data structure into which the associated data can be spanned from the current pages, where the at least one additional page is allocated from the pool of available memory pages in accordance with a fullness threshold for the data structure.

Flexible sizing for data buffers

Methods and devices for rendering graphics in a computer system include a graphical processing unit (GPU) with a flexible, dynamic, application-directed mechanism for varying the rate at which fragment shading is performed for rendering an image to a display. In particular, the described aspects include determining, at a rasterization stage, map coordinates based on coarse scan converting a primitive of an object, the map coordinates indicating a location on a sampling rate parameter (SRP) map of a fragment within the primitive of the object, and identifying a lookup value for the fragment within the primitive of the object based at least on map coordinates, and calculating a respective fragment variable SRP value for the fragment within the primitive of the object based at least on the lookup value.

Variable rate shading

Methods and devices for managing first-in first-out (FIFO) queues in graphics processing are described. A write operation can be executed by multiple write threads on a graphics processing unit (GPU) to write data to memory locations in the multiple pages of memory. Similarly, and/or simultaneously, a read operation can be executed by multiple read threads to read data from the memory locations. The write and read operations include updating a pointer or multiple pointers indicating the point at which all preceding data has been fully written, or fully read. The read and write operations can also include maintaining and advancing one or more allocation pointers, and performing comparisons with the read and write done pointers, and/or various methods of synchronization, to handle overflow and underflow scenarios, to ensure read operations only read valid data, and write operations do not attempt to write to locations which are already in use.

Techniques for safely and efficiently enqueueing and dequeueing data on a graphics processor

Methods and devices for managing first-in first-out (FIFO) queues in graphics processing are described. A write operation can be executed by multiple write threads on a graphics processing unit (GPU) to write data to memory locations in the multiple pages of memory. The write operation can also include allocating additional pages of memory for the FIFO queue where a write allocation pointer is determined to achieve a threshold, such to grow the FIFO queue before the memory is actually needed for writing. Similarly, comprises a read operation can be executed by multiple read threads to read data from the memory locations. The read operation can also include deallocating pages of memory back to a memory pool where a read done pointer is determined to achieve a threshold, such as an end of a page.

Methods and devices for rendering graphics in a computer device include receiving, at a graphics processing unit (GPU), a memory location address of a portion of a primitive to be rendered along with an indication of one or more values of one or more pixel shader parameters for the portion of the primitive, selecting, by the GPU, a pixel shader from a plurality of possible pixel shaders based on the indication of the one or more values of the one or more pixel shader parameters, and generating, by the GPU, at least one output of a render target of the portion of the primitive based on applying the pixel shader to the portion of the primitive.

Multiple shader processes in graphics processing

Enhanced data buffer control in data systems is presented herein. In one example, a method of handling data buffer resources in a graphics processor includes establishing a pool of available memory pages tracked by memory pointers for use in a growable data structure. Responsive to requests by at least a shader unit of the graphics processor for space in the growable data structure in which to write shader data, the method includes providing to the shader unit at least write pointers to locations within memory pages from the growable data structure in accordance with data sizes indicated in the requests. Responsive to exceeding a threshold fullness of the growable data structure, the method includes allocating at least one further memory page from the pool of available memory pages for inclusion in the growable data structure.

Flexible buffer sizing in graphics processors

Methods and devices for rendering graphics in a computer system include a graphical processing unit (GPU) with a flexible, dynamic, application-directed mechanism for varying the rate at which fragment shading is performed for rendering an image to a display. In particular, the described aspects allow different shading rates to be used for different regions of a primitive based on a new, interpolated shading rate parameter. In other words, the described aspects enable the GPU to change shading rates on-the-fly between different fragments of each primitive. Additionally, or independently, the GPU utilizes each respective shading rate parameter to determine how many sample positions to consider to be covered by the computed shaded output, e.g., the fragment color, thereby allowing the color sample to be shared across two or more pixels.

Methods and devices for testing graphics hardware may include reading content of a selected capture file from a plurality of capture files. The methods and devices may include transferring content from the selected capture file to an emulator memory of an emulator separate from the computer device. The methods and devices may include executing at least one pseudo central processing unit (pseudo CPU) operation to coordinate the execution of work on a graphics processing unit (GPU) of the emulator using the content from the selected capture file to test the GPU. The methods and devices may include receiving and store rendered image content from the emulator when the work is completed.

Execution of graphic workloads on a simulated hardware environment

Methods and devices for graphics shading in a computing device. The methods and devices may include receiving a respective cache line of a plurality of cache lines of a shader stored in a memory, wherein the respective cache line and one or more other ones of the plurality of cache lines include at least one jump instruction. Further, the methods and devices may include executing the respective cache line of the shader and skipping to a next portion of the plurality of cache lines based on the at least one jump instruction. Moreover, the methods and devices may include executing one or more prefetchers contemporaneously with the shader in response to the at least one jump instruction, each prefetcher requesting a subsequent one of the plurality of cache lines from the memory, wherein each prefetcher corresponds to a respective jump instruction.

Prefetching for a graphics shader

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Jason Matthew Gould