Apple Inc.

Jason M Kassoff

Brian P Lilly

Gurjeet S Saund

Ruchi Wadhawan

George Kong Yiu

Kevin C Wong

Erik P Machnicki

Shane J Keil

Andrew J Beaumont-Smith

James Vash

Aditya Kesiraju

Derek R Kumar

Tyler J Huberty

Munetoshi Fukami

Ran A Chachick

Krishna C Potnuru

Rajdeep L Bhuyar

Chaitanya Kosaraju

Erdem Guleyupoglu

Sandeep Kumar Gupta

Hao Chen

Wei-Han Lien

John H Mylius

Shih-Chieh Wen

Conrad Havluj Ziesler

Prashant Jain

A system may include a plurality of processors and a coprocessor. A plurality of coprocessor context priority registers corresponding to a plurality of contexts supported by the coprocessor may be included. The plurality of processors may use the plurality of contexts, and may program the coprocessor context priority register corresponding to a context with a value specifying a priority of the context relative to other contexts. An arbiter may arbitrate among instructions issued by the plurality of processors based on the priorities in the plurality of coprocessor context priority registers. In one embodiment, real-time threads may be assigned higher priorities than bulk processing tasks, improving bandwidth allocated to the real-time threads as compared to the bulk tasks.

Coprocessor context priority

Techniques are disclosed relating to set-associative caches in processors. In one embodiment, an integrated circuit is disclosed that includes a set-associative cache configured to receive a request for a data block stored in one of a plurality of ways within the cache, the request specifying an address, a portion of which is a tag value. In such an embodiment, the integrated circuit includes a way prediction circuit configured to predict, based on the tag value, a way in which the requested data block is stored. The integrated circuit further includes a tag array circuit configured to perform a comparison of a portion of the tag value with a set of previously stored tag portions corresponding to the plurality of ways. The tag array circuit is further configured to determine whether the request hits in the cache based on the predicted way and an output of the comparison.

Cache way prediction

A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

Interfacing dynamic hardware power managed blocks and software power managed blocks

A system and a method which include one or more processors, a memory coupled to at least one of the processors, a communication link coupled to the memory, and a power management unit. The power management unit may be configured to detect an inactive state of at least one of the processors. The power management unit may be configured to disable the communication link at a time after the processor enters the inactive state, and disable the memory at another time after the processor enters the inactive state.

L2 flush and memory fabric teardown

Systems and methods for managing fast to slow links in a bus fabric. A pair of link interface units connect agents with a clock mismatch. Each link interface unit includes an asynchronous FIFO for storing transactions that are sent over the clock domain crossing. When the command for a new transaction is ready to be sent while data for the previous transaction is still being sent, the link interface unit prevents the last data beat of the previous transaction from being sent. Instead, after a delay of one or more clock cycles, the last data beat overlaps with the command of the new transaction.

Managing fast to slow links in a bus fabric

A system and method for dithering a clock signal during idle times is disclosed. An integrated circuit (IC) includes a number of functional units and a clock tree. The clock tree includes a root level clock-gating circuit, a number of regional clock-gating circuits, and a number of leaf level clock-gating circuits. The root level clock-gating circuit is coupled to distribute an operating clock signal to the regional clock-gating circuits, while the regional clock-gating circuits are each configured to distribute the operating clock signal to correspondingly coupled ones of the leaf level clock-gating circuits. The IC may further include a control unit configured to monitor activity levels and indications from each of the functional units. The control unit may cause the root clock-gating circuit to dither the clock signal if the IC is idle, wherein dithering includes reducing the duty cycle and the effective frequency of the operating clock signal.

Regional clock gating and dithering

In an embodiment, a memory port controller (MPC) is coupled to a memory port and receives transactions from processors and a coherency port (ACP) used by one or more peripheral devices that may be cache coherent. The transactions include various quality of service (QoS) parameters. If a high priority QoS transaction is received on the ACP, the MPC may push previous (lower priority) transactions until the high priority transaction may be completed. The MPC may maintain a count of outstanding high priority QoS transactions. The L2 interface controller and ACP controller may push increment and decrement events based on processing the high priority QoS transactions, and the MPC may push the memory transactions when the count is non-zero. In an embodiment, the MPC may continue pushing transactions until the L2 interface controller informs the MPC that the earlier transactions have been completed.

Push mechanism for quality of service (QoS) support in coherency port

In an embodiment, a system includes a memory controller, processors and corresponding caches. The system may include sources of uncertainty that prevent the precise scheduling of data forwarding for a load operation that misses in the processor caches. The memory controller may provide an early response that indicates that data should be provided in a subsequent clock cycle. An interface unit between the memory controller and the caches/processors may predict a delay from a currently-received early response to the corresponding data, and may speculatively prepare to forward the data assuming that it will be available as predicted. The interface unit may monitor the delays between the early response and the forwarding of the data, or at least the portion of the delay that may vary. Based on the measured delays, the interface unit may modify the subsequently predicted delays.

Critical word forwarding with adaptive prediction

In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.

Cache used both as cache and staging buffer

Growing community of inventors

Denver, CO, United States of America

Jason M Kassoff