Intel Corporation

Jason M Fung

Gyan Prakash

Selim Aissi

Abhishek Basak

Mojtaba Mirashrafi

Jiphun C Satapathy

Mrudula Yelamanchi

Dave Paul Singh

Sachin B Godse

Nagaraju N Kodalapura

Arun Kanuparthi

Cris Rhodes

Neer Roggel

Chen Liu

Abhishek Chakraborty

The technology disclosed herein determining one or more vulnerable instructions in workload code and determining one or more additional instructions to be inserted in the workload code based at least in part on a power model of a system bus of a processor, when a power model of a processor is dependent on an order of instructions of workload code, inserting the one or more additional instructions with dependency to the workload code to produce complementary power consumption of the system bus to power consumption of the system bus from executing the one or more vulnerable instructions; and when the power model is not dependent on the order of instructions of workload code, inserting the one or more additional instructions without dependency to the workload code to produce complementary power consumption of the system bus to power consumption of the system bus from executing the one or more vulnerable instructions.

Code-based technique to mitigate power telemetry side-channel leakage from system buses

A system may include a processor and a memory, the processor having at least one cache. The cache may include a plurality of sets, each set having a plurality of cache lines. Each cache line may include several bits for storing information, including at least a 'shared' bit to indicate whether the cache line is shared between different processes being executed by the processor. The example cache may also include shared cache line detection and eviction logic. During normal operation, the cache logic may monitor for a context switch (i.e., determine if the processor is switching from executing instructions for a first process to executing instructions for a second process). Upon a context switch, the cache logic may evict the shared cache lines (e.g., the cache lines with a shared bit of 1). This eviction of shared cache lines may prevent attackers utilizing such attacks from gleaning meaningful information.

Hardware based technique to prevent critical fine-grained cache side-channel attacks

Disclosed in some examples are methods, systems, and machine readable mediums which provide a security rating to an STA for a WLAN AP. Prior to connecting to an AP, the STA employs pre-connection logic in the STA to identify likely safe and likely unsafe APs. Once the user connects to an AP, the STA connects first in an untrusted mode. In the untrusted mode, the STA uses the network connectivity provided by the AP to establish a secure connection to a network-based WLAN trust service for post-connection security checks. If the AP passes the post-connection security checks, the STA may allow other applications to access the network connection provided by the AP.

Wireless hotspot attack detection

A device, system, and method for providing processor-based data protection on a mobile computing device includes accessing data stored in memory with a central processing unit of the mobile computing device and determining that the accessed data is encrypted data based on a data included in one or more control registers of the central processing unit. If the data is determined to be encrypted data, the central processing unit is to decrypt the encrypted data using a cryptographic key stored in the central processing unit. The encrypted data may also be stored on a drive of the mobile computing device. The encryption state of the data stored on the drive is maintained in a drive encryption table, which is used to update a memory page tables and the one or more control registers.

Device, system, and method for processor-based data protection

Growing community of inventors

Portland, OR, United States of America

Jason M Fung