Texas Instruments Corporation

Jason Lynn Peck

Gary A Cooper

Markus Koesler

Joseph Raymond Michael Zbiciak

Gary L Swoboda

Amritpal Singh Mundra

Jose Luis Flores

Chunhua Hu

Venkateswar Reddy Kowkutla

Anthony J Lell

Rejitha Nair

John Chrysostom Apostol

Kazunobu Shin

Siva Srinivas Kothamasu

Raghavendra Santhanagopal

Anthony Frederick Seely

Nishanth Menon

Rajesh Kumar Vanga

Joseph R Zbiciak

Byran Thome

Embodiments include a device having a processor core that can operate in any of multiple operating modes, and a controller that issues a debug request to the processor core. The processor core includes a register configured to store current operating state information of the processor core. The debug request includes a first portion to specify a virtual machine qualifier with respect to servicing the debug request, a second portion to specify a processor core operating mode qualifier with respect to servicing the debug request, and a third portion to specify a function qualifier with respect to servicing the debug request. Each qualifier can be enabled to make the qualifier a condition of servicing the debug request. When all enabled qualifiers are satisfied, the processor core services the debug request. The servicing of the debug request may be performed in real-time without suspending the processing device.

Context-sensitive debug requests for memory access

A system, e.g., a system on a chip (SoC) includes a first domain including a first processor configured to boot the system; a second domain including a processing subsystem having a second processor; and isolation circuitry between the first domain and the second domain During boot-up of the system, the first processor provides code to the second domain. When the code is executed by the second processor, it configures the processing subsystem as either a safety domain or as a general-purpose processing domain. The safety domain may an external safety domain or an internal safety domain.

System on a chip with an integrated configurable safety master microcontroller unit

A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without 'breaking' the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.

Managing and maintaining multiple debug contexts in a debug execution mode for real-time processors

Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.

Integrated circuit with debugger and arbitration interface

Devices and methods are provided for identifying a debug event associated with a data element of a data stream, and performing debugging when a processor executes a software program in connection with the data stream. The debug event is tracked through a data pipeline to the processor. In an embodiment, the debug event is acted on only when the processor is ready to consume the data element associated with the debug event. In an embodiment, the debug event is determined by monitoring iteration counts of loop counters associated with an address generator and comparing the iteration counts to respective stored count values.

Tracking debug events from an autonomous module through a data pipeline

A system on a chip (SoC) includes a first domain comprising a first processor configured to boot the SoC, and a first debug subsystem, a second domain comprising a second processor, the second domain configurable as either a safety domain or a general-purpose processing domain, and isolation circuitry between the first domain and the second domain. During boot-up of the SoC, the first processor provides code to the second domain which, when executed by the second processor, configures the second domain as either a safety domain or as a general-purpose processing domain.

An integrated circuit includes: a debugger; and an interface coupled to the debugger. The interface has: arbitration logic coupled to the debugger; a power processor coupled to the arbitration logic; and a power management network coupled to the power processor. The integrated circuit also includes subsystems coupled to the interface. The debugger is configured to perform debugging operations of the subsystems via the interface.

Disclosed embodiments include a processing device having a debug controller that issues a context-sensitive debug request. The context-sensitive debug request includes at least one conditional criteria. A processing core receives the debug request, determines whether all of the at least one conditional criteria are true, and services the debug request when all of the at least one conditional criteria are true by accessing a data location indicated in the debug request. The servicing of the debug request may be performed in real-time mode without suspending the processing device, and the accessing can be a read or a write operation depending on the type of access indicated in the debug request. The conditional criteria may include one or more of a processor mode condition, a virtual machine identifier condition, and a debug context condition.

A method for debugging a software program is provided when the software program is executed on a processor. An asynchronous debug event is detected. The asynchronous debug event is tracked through a data pipeline to the processor. In one embodiment, the asynchronous debug event is acted on only when the processor is ready to consume a data element associated with the asynchronous debug event.

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Houston, TX, United States of America

Jason Lynn Peck