International Business Machines Corporation

Jason Lee Frankel

Paul Robert Walling

Franklin M Baez

Sungjun Chun

Suresh D Kadakia

Mukta G Farooq

David Clifford Long

Benjamin V Fasano

Roger Donell Weekly

Sudipta Kumar Ray

Frank Louis Pompeo

Jean Audet

Jinwoo Choi

Harvey Charles Hamel

Daniel Mark Dreps

Sarah Huffsmith Knickerbocker

Andreas H A Arp

Glenn Graham Daves

Herbert I Stoller

Chad Andrew Marquart

William Frederick Shutler

Douglas J Malone

Kenneth A Bird

Ching Lung Tong

John F Vetrero

Kenneth A Papae

Lily Jielu Zhang

Anthony Wayne Sigler

Cathy Ann Zadany

Eric Vance Kline

Anand Haridass

Erich Klink

Peter Jeffrey Brofman

Harsaran S Bhatia

Anson Jay Call

Marie S Cole

Michael S Cranmer

Brian Leslie Singletary

Marek Andrzej Orlowski

Francis F Cappo

Ahmed Sayeed Shah

Kevin Grosselfinger

John A Ludwig

Scott A Sikorski

Myra Muth Boenke

Deana Cosmadelis

Roxan Lemire

Alain Ayotte

Alice L Donaldson

Rafael Perez-Acevedo

C Timothy Ryan

Gilles Poitras

A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module

Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.

Semiconductor package floating metal checks

A method of performing automated surface-mount package design includes obtaining physical inputs that include names and locations of top and bottom pins, and obtaining electrical inputs that include electrical parameters such as impedance. The method also includes automatically performing analysis and processing of the physical inputs and the electrical inputs. A design file for manufacture of the surface-mount package is automatically generated based on the performing the analysis and the processing. The design file specifies a number and material of layers of the surface-mount package.

Automated generation of surface-mount package design

A computer system receives an initial multilayered ceramic package design. The computer system maintains a first selection of mesh line segments of the mesh line segments at a first width and adjusts a second selection of mesh line segments of the plurality of mesh line segments to a second width. The computer system controls fabrication of the multilayered ceramic package based on the modified multilayered ceramic package design.

Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures

A first selection of mesh line segments of a mesh layer are of a first width and a second selection of mesh line segments of the mesh layer are of a second width, wherein the second width is greater than the first width. The second selection of mesh line segments of the second width are positioned in parallel to a selection of signal lines in a signal layer that are likely to introduce crosstalk, wherein the widening of the mesh line segments shadowing the selection of signal lines increases the likelihood that the return current associated with the signal will flow in the wider mesh line segment, thereby increasing the likelihood of containing the electromagnetic fields associated with the signal such that crosstalk to other signals is reduced or contained.

A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier; one or more integrated circuit chips attached to a top surface of the chip carrier; a ceramic-based cap structure attached to the top surface of the chip carrier, and covering the one or more integrated circuit chips; and a conductive grid structure embedded within the chip carrier and the cap structure, the conductive grid structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction; wherein the conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

Structure for implementing secure multichip modules for encryption applications

A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

Method and structure for implementing secure multichip modules for encryption applications

A system and method for reducing noise in a multi-layer ceramic package are provided. With the system and method, additional shielding wires are inserted into the reference planes wherever there are no signal vias present. These additional lines in the reference planes force stronger signal interaction with the reference (vdd/gnd) thereby reducing the interaction between the signals in the signal layers. As a result, the noise present in the signals of the signal layers is reduced.

System and method for noise reduction in multi-layer ceramic packages

A structure for a system of chip packages includes a master substrate and at least one subset substrate of the master substrate. The subset substrate includes a portion of the master substrate that has an identical pin out pattern as the portion of the master substrate. The subset substrate has identical internal net lists as the portion of the master substrate. The subset substrate is adapted to accommodate a smaller chip than the master substrate. The master substrate is the largest substrate in the system. The invention also prepares a system of chip packages. The invention selects a master substrate and then selects a subset substrate of the master substrate.

Nested design approach

A method, system and program product implementing storage of a (power or ground) mesh plane file using a multiple line shape, possibly with the storage of lines also, to reduce file size. In addition, the invention implements an activate-substantial-portion-and-remove technique to generate mesh planes rather than the conventional additive approach, which improves the speed of designing the IC carriers. A resulting mesh plane design file may be as much as half the size of a file generated using the conventional line-by-line and storage approaches.

Mesh plane generation and file storage

A jogging structure for translating wiring connections from points in a first grid to corresponding points in a second grid in a chip carrier module is disclosed. In an exemplary embodiment, the structure includes a first translation layer, coupled to the first grid, the first translation layer translating the first grid in an x-axis direction. A second translation layer is coupled to the first translation layer, the second translation layer for translating said wiring connections from the first grid in a y-axis direction, the y-axis direction being orthogonal to the x-axis direction. The second translation layer is further coupled to the second grid.

Jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modules

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Wappingers Falls, NY, United States of America

Jason Lee Frankel