United Microelectronics Corp.

Jason Jyh-Shyang Jenq

Hal Lee

A method for fabricating a gate electrode is disclosed. The present invention is provided a method to utilize the first nitrogen-containing RTP treatment to treat the substrate to form a first barrier layer thereon. Then, the dielectric material has high dielectric constant that is deposited on the first barrier layer to improve the thermal stability and chemical stability of the semiconductor substrate. Next, a second barrier layer and a metal gate layer are sequentially formed on the dielectric layer. After a photolithography process, a gate electrode is formed on the semiconductor substrate. Thereafter, a surface inhibition layer is formed on sidewall of the gate electrode to improve the resistivity and thermal stability for metal gate layer after a second nitrogen-containing RTP treatment is performed on the gate electrode.

Method for fabricating a gate electrode

In the present invention, a method of forming multitude of growth rates of oxide layer on the surface of a substrate is provided. The method comprises providing a first oxide layer on the substrate. A photoresist layer is formed on the first oxide layer. The photoresist layer exposes a portion of the first oxide layer. The exposed portion of the first oxide layer is subjected to plasma fluoridation. Then the photoresist layer is removed. Again, the first oxide layer is removed and a second oxide layer is formed on the substrate.

Method for forming oxide layers with different thicknesses

A method for forming an integrated circuit device that incorporate both an array of memory cells and an array of logic circuits on a single chip or substrate is disclosed. The substrate has a transfer field effect transistor (FET) with a first gate electrode and a first source/drain region formed in and on a embedded DRAM region of the substrate and has a logic FET with a second gate electrode and a second source/drain region formed in and on a logic circuit region of the substrate. Next, a dielectric layer was deposited over the exposing surface of said transfer FET and above of the logic FET. Moreover, the dielectric layer was polished until upper surface of the first gate electrode and the second gate electrode is exposed. Subsequently, a photoresist layer is formed over the dielectric layer and the first gate electrode. And then the dielectric layer was etched until upper surface of the logic FET is exposed. Next, the photoresist layer was removed. Finally, a self-aligned silicide layer was deposited simultaneously over the exposed second gate electrode, over the second source/drain region and over the exposed first gate electrode.

Growing community of inventors

Ping-Tong, Taiwan

Jason Jyh-Shyang Jenq