Raytheon Company

Aspen Aerogels, Inc.

Kelvin Thermal Technologies, Inc.

Ratheon Company

Jason G Milne

John J Drab

Clifton Quan

Christopher R Koontz

Fangchou Yang

Tse E Wong

Avery Y Quil

George Leighton Gould

Jar Jar Lee

Yung-Cheng Lee

Susan C Trulli

Robert S Isom

David H Altman

John Paul Gianvittorio

Mark S Hauhe

William J Davis

Kevin C Rolston

Allen T Wang

Terry C Cisco

Robert B Hallock

Anurag Gupta

Mary A Teshiba

Ward G Fillmore

Alec Ekmekji

Paul Nahass

Frederick A Dominski

Jason M Kehl

Nick Zafiropoulos

Andrew J Marquette

Yiwen Zhang

Alec Ekrnekjl

Allen T S Wang

Aaron George

Steve F Mayrose

Allen TS Wang

Nick Zafiropoulous

Methods and apparatus for providing an assembly including a base substrate, a lid substrate, and a ring frame between the base substrate and the lid substrate to define a protected volume, where the ring frame includes through vias. A die may be contained in the protected volume. Sensor circuitry can include conductive pillars in the protected volume and the die can include circuity to determine an impedance of the pad and the pillars for tamper detection. An edge cap can be coupled to at least one side of the assembly for tamper detection.

Die package having security features

Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.

Die encapsulation in oxide bonded wafer stack

In one aspect, a unit cell of a phased array antenna includes a metal plate having a hole, a first side and a second side opposite the first side, a first plurality of laminate layers disposed on the first side, a second plurality of layers disposed on the second side of the metal plate, a radiator disposed in the first plurality of layer on the first side, a feed circuit disposed in the second plurality of laminate layers on the second side and configured to provide excitation signals to the radiator and a first plurality of vias extending through the hole connecting the feed circuit to the radiator.

High frequency polymer on metal radiator

In one aspect, an active electronically scanned array (AESA) tile includes a radiator structure and oxide-bonded semiconductor wafers attached to the radiator structure and comprising a radio frequency (RF) manifold and a beam former. An RF signal path through the oxide-bonded wafers comprises a first portion that propagates toward the beam former and a second portion that propagates parallel to the beam former.

Tile for an active electronically scanned array (AESA)

A heat dissipation structure for a semiconductor integrated circuit die having a plurality of connection areas may include a thermal mount comprising a plurality of pillars each having an aspect ratio preferable greater than 2:1 and each positioned to connect to one of the connection areas on a peripheral portion of the semiconductor integrated circuit die with one of a plurality of interface layers. A thermal conductivity of materials for the connection areas, the thermal mount, the pillars, each of which is preferably copper, and the interface layers, which are preferably copper nanoparticle layers, has a thermal conductivity greater than 100 Watts per meter degree Kelvin (W/m&#xb7;K). Flexure of the pillars accommodates mechanical strain arising from temperature changes and differences in coefficients of thermal expansion for materials of the semiconductor integrated circuit die and the thermal mount.

Mechanically improved microelectronic thermal interface structure for low die stress

A heat-dissipating device includes at least one heat-dissipating surface and a micro-sized cooling mechanism formed directly on the heat-dissipating surface by an additive manufacturing process. The cooling mechanism includes at least one fluid passage, such as a micro-hose, for carrying a cooling medium from a coolant source directly to the heat-dissipating surface. The cooling mechanism is fluidly sealed to the heat-dissipating surface such that the cooling medium is in thermal contact directly with the heat-dissipating surface.

Micro-hoses for integrated circuit and device level cooling

A coincident phased dual-polarized antenna array configured to emit electromagnetic radiation includes: a plurality of electromagnetic radiators arranged in a grid, the plurality of electromagnetic radiators defining a plurality of notches; a ground plane spaced from the electromagnetic radiators; a conductive layer disposed between the electromagnetic radiators and the ground plane, the conductive layer having a plurality of slots laterally offset from the notches and being spaced apart from and electrically insulated from the electromagnetic radiators; and a plurality of feeds, each of the feeds spanning a corresponding slot of the slots and electrically connected to a portion of the conductive layer at one side of the corresponding slot.

Short coincident phased slot-fed dual polarized aperture

A coolant distribution structure for an MMIC having: an input/output layer with an input port for receiving a coolant for transmission to coolant channels in the MMIC and an output port for exiting the coolant after such coolant has cooled active devices in the MMIC, a coolant pass-through layer to receive the coolant from the input port and having structure to inhibit such received coolant from passing directly to the output port, a coolant distribution layer for receiving coolant passing from the coolant pass-through layer and distributing such received coolant to the cooling channels to absorb heat generated by the active devices and then directing heated coolant to the coolant distribution layer and out of the porting layer via the pass-through layer. The coolant pass-through layer has a structure configured to inhibit such heated coolant from passing directly to the input port prior to such heated absorbed coolant being transmitted to the output port.

Coolant distribution structure for monolithic microwave integrated circuits (MMICs)

A circuit board assembly includes a circuit board, a chip attached to the circuit board and a dielectric layer. The chip has a circuit facing the circuit board and spaced from it. The dielectric layer includes an aerogel. In one embodiment, the aerogel has a dielectric constant of approximately 2.0 or less and a compression strength of at least approximately 100 psi.

Aerogel dielectric layer

An RF module including transmitting, receiving, and processing elements, capable of operating in a standalone mode or as part of an array of similar or identical modules. The RF module includes a radiator (), transmit-receive circuitry (), a digital receiver-exciter (), a processor (), and a data interface (). The processor is configured to exchange in-phase and quadrature data with other processors in an array, so that, when configured as an array, digital transmit beam forming and receive beam forming are possible.

RF puck

A wafer assembly with internal fluid channels. The assembly is fabricated by creating one or more channels in a first surface of a first semiconductor wafer and creating an oxide surface on the first surface of the first semiconductor wafer. An oxide surface is also created on a first surface of a second semiconductor wafer. The assembly is fabricated by bonding the oxide surface of the first surface of the first semiconductor wafer to the oxide surface of the first surface of the second semiconductor wafer to create a wafer assembly and to seal the one or more channels at edges defined by the bonded first and second surfaces.

Stacked wafer with coolant channels

A package and method for packaging a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices.

Method for packaging semiconductors at a wafer level

Provided herein are devices, systems and techniques for establishing a variable height conformal antenna array having a planar backplane. More particularly, positioning of radiating elements can be made insensitive to variable ground height by selecting a suitable radiating element, such as a flared notch and arranging them to have a profile such that their outer extremities are positioned along a conformal, curved shape. Differences in radiator heights can be taken up by the addition of parallel vertical ground planes disposed between the radiating elements and the backplane. Adjacent vertical ground planes effectively form cutoff waveguide sections that naturally isolate the backplane from the radiating elements. The vertical ground planes edges effectively form a virtual curved ground for the radiating elements, following curvature of the array profile. Accordingly, heights of radiating elements are uniform with respect to the virtual ground, while being allowed to vary with respect to the backplane.

Variable height radiating aperture

Methods for assembling an active array system are described. In one exemplary embodiment, an active subarray panel assembly having a first surface with a first array of electrical contacts and a radiator aperture with an array of radiator structures and an aperture mounting surface with a second array of electrical contacts are assembled together. The first surface of the panel assembly and the aperture mounting surface of the radiator aperture are brought into contact with an adhesive layer including microwave interconnects in a pattern corresponding to the first array of electrical contacts and the second array of electrical contacts so that the adhesive layer is between the first surface of the panel assembly and the aperture mounting surface of the radiator aperture. Pressure, heat and vacuum are applied to cure the adhesive and complete engagement of the microwave interconnects.

Growing community of inventors

Hawthorne, CA, United States of America

Jason G Milne