Globalfoundries Inc.

Globalfoundries U.S. Inc.

Jason Eugene Stephens

Guillaume Bouche

Tuhin Guha Neogi

Jongwook Kye

Mark Alexander Zaleski

Andy Chih-Hung Wei

Lei Yuan

Roderick Alan Augur

David C Pritchard

Jia Zeng

Marc Laurent Tarabbia

Craig Child

Vikrant Kumar Chauhan

Mahbub Rashed

Suresh Venkatesan

Subramani Kengeri

Yunfei Deng

Irene Y Lin

Yuansheng Ma

Sudharshanan Raghunathan

Byoung Youp Kim

Nader Magdy Hindawy

David Michael Permana

Andy Chi-Hung Wei

Ruilong Xie

Lars W Liebmann

Hsueh-Chung Chen

Shreesh Narasimha

Andy C Wei

Daniel Chanemougame

Terry Allen Spooner

Shibly S Ahmed

Gregory Allen Northrop

Deniz Elizabeth Civay

Martin O'Toole

Rod Augur

Irene Yuh-Ling Lin

Yuan Lei

Lawrence Alfred Clevenger

Albert Manhee Chu

Harry Jay Levinson

Ning Lu

Li Ping Yang

Scott C Johnson

Xiang Hu

Richard Farrell

David E Brown

Linus Jang

Akshey Sehgal

David Doman

Soo Han Choi

Chinh Nguyen

Lixia Lei

Kai Sun

Jeff Kim

Ahmed Hassan

Patrick Ryan Justison

Shyam Pal

Jiong Li

Ingolf Lorenz

Terry J Bordelon

Seung-Hyun Rhee

Anbu Selvam K M Mahalingam

James B Gullette

Jagannathan Vasudevan

Abbas Guvenilir

Jongwook K E

Larry Ho

The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

Middle of the line self-aligned direct pattern contacts

The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.

Merge mandrel features

At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

Methods, apparatus and system for a passthrough-based architecture

Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.

Devices and methods for forming cross coupled contacts

At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one Mmetal structure void is formed. At least one CB structure void adjacent the Mmetal structure void is formed. An etch process is performed the Mand CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M, CB, and CA structure voids are metallized.

Method, apparatus and system for a high density middle of line flow

Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias

Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

Transistor contacts self-aligned in two dimensions

A method including providing a semiconductor structure having a dielectric stack, hardmask stack, and mandrel layer disposed thereon. An array of mandrels is patterned into the mandrel layer. Mandrel spacers are formed self-aligned on sidewalls of the mandrels. A gapfill layer is disposed and planarized over the semiconductor structure. Non-mandrel pillars are formed over the planarized gapfill layer. Exposed portions of the gapfill layer are etched to form non-mandrel plugs preserved by the pillars. The pillars are removed to form a pattern, the pattern including the non-mandrel plugs. The pattern is utilized to form an array of alternating mandrel and non-mandrel metal interconnection lines in the dielectric stack. The array includes non-mandrel dielectric structures formed from the non-mandrel plugs.

Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit

A method includes forming first and second contact openings in a first dielectric layer. At least the first contact opening is at least partially lined with a liner layer. A first conductive feature is formed in the first contact opening and a second conductive feature is formed in the second contact opening. A portion of the liner layer adjacent a top surface of the first dielectric layer is removed to define a recess. A barrier layer is formed above the first dielectric layer and in the recess. The barrier layer has a first dielectric constant greater than a second dielectric constant of the first dielectric layer. A second dielectric layer is formed above the barrier layer. A third conductive feature is formed embedded in the second dielectric layer and contacting the second conductive feature.

Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices

A method includes providing a structure having a first hardmask layer, second hardmask layer and mandrel layer disposed respectively over a dielectric stack. An array of mandrels is patterned into the mandrel layer. A gamma trench is patterned into the second hardmask layer and between the mandrels. Self-aligned inner spacers are formed on sidewalls of the gamma trench, the inner spacers forming a portion of a pattern. The pattern is etched into the dielectric stack to form an array of alternating mandrel and non-mandrel metal lines extending in a Y direction and being self-aligned in a perpendicular X direction. The portion of the pattern formed by the inner spacers is utilized to form a pair of non-mandrel line cuts in a non-mandrel line. The non-mandrel line cuts are self-aligned in the Y direction.

Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines

A method includes providing a structure having a first, second and third hardmask layer and a mandrel layer disposed respectively over a dielectric stack. An array of mandrels, a beta trench and a gamma trench are patterned into the structure. First inner spacers are formed on sidewalls of the beta trench and second inner spacers are formed on sidewalls of the gamma trench. The first and second inner spacers form a portion of a pattern. The pattern is etched into the dielectric stack to form an array of mandrel and non-mandrel metal lines extending in a Y direction and being self-aligned in an X direction. The portion of the pattern formed by the first and second inner spacers forms a first pair of cuts in a mandrel line and a second pair of cuts in a non-mandrel line respectively. The cuts are self-aligned in the Y direction.

Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal lines

A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.

Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit

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Menands, NY, United States of America

Jason Eugene Stephens