International Business Machines Corporation

Infineon Technologies North America Corp.

Jason Edward Rotella

David W Milton

David James Hathaway

Douglas Willard Stout

Reid A Wistort

Ivan L Wemple

Thomas B Chadwick, Jr

Fred John Towler

Margaret R Charlebois

Sebastian Theodore Ventrone

John Atkinson Fifield

Albert Manhee Chu

Clarence Rosser Ogilvie

John P Connor

Paul Mark Schanely

Patrick R Hansen

Jean-Marc Dortu

Gerald P Pomichter

W Riyon Harding

Steven Leschuk

A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second clock signal using the first clock signal; detecting coincident edges of the first and the second clock signals; and changing the second frequency to a third frequency different from the second frequency upon detection of the coincident edges.

Method and circuit for dynamically changing the frequency of clock signals

A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

Static timing slacks analysis and modification

A method and apparatus for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.

Method and apparatus for transmitting data in an integrated circuit

Method for dynamically changing the frequency of clock signals

A match line circuit in a content addressable memory (CAM) has a match line coupled to a first pull-up device and a first pull-down device at a match node. The first pull-up device has selectively adjustable pull-up impedances associated with it. The match line circuit also includes a second pull-up device coupled to a second pull-down device at a float node, and an enabling signal for activating the match line circuit during a memory comparison operation. The enabling signal precharges the match node to a logic low level and the float node to a logic high level in between memory comparison operations.

Content addressable memory (CAM) having a match line circuit with selectively adjustable pull-up impedances

A Sequential Gray Code to Thermometer Code decoder circuit adapted for area efficient use at each pad of an integrated circuit chip for incrementally adjusting a digitally adjustable resistance for continuous or periodic adjustment of on-chip terminations. The sequential decoder for decoding a Gray code count to a T-bit Thermometer code count is constructed of a plurality (T) of cascaded decoder cells, each cell sensing the state of only one bit of the Gray code count. The decoder cells are cascaded to from decoding-latching stages each stage responsive to an individual one of single-bit changes between consecutive counts in the Gray code. Each stage contains a decoding-latching circuit adapted to detecting and latching the occurrence of one single-bit change in the Gray code.

Area efficient, sequential gray code to thermometer code decoder

A method for determining a desired operating impedance for a computer memory circuit includes applying, to a reference circuit, a test impedance value to a reference circuit. The test impedance value is controlled by a binary count. A determination is made, based upon the applied test impedance value, whether the reference circuit is in either a first state or a second state. The binary count is incremented if the reference circuit is in the first state and decremented if the reference circuit is in the second state. A condition is determined in which the reference circuit oscillates between the first state and said second state, and a pair of binary count values is stored. The desired operating impedance for the computer memory circuit corresponds to the lower of the stored pair of binary count values.

Method and apparatus for adjusting control circuit pull-up margin for content addressable memory (CAM)

An adjustable clock multiplier circuit is disclosed which is believed to be of advantage for inexpensively and locally generating an adjustable high frequency clock, such as may be useful for built-in self test of an embedded memory element of a digital logic integrated circuit. The clock multiplier circuit uses a pulse generator of the monostable type to generate a pulse in response to the leading edge of an input clock signal. The pulse is delayed through a programmable delay circuit and then provided as a feedback input to the pulse generator. In such manner, an output clock signal comprised of a train of pulses is generated during a cycle of the input clock signal. A counter increments a count in response to pulses generated in this way. When the pulse count is too high, a limiter outputs an ADJUST DOWN signal which slows down the output cycle time of the clock multiplier. When the pulse count is too low, the limiter outputs an ADJUST UP signal which speeds up the output cycle time of the clock multiplier. The ADJUST DOWN/UP signals are preferably provided to a register which maintains and outputs a string of control signals for controlling a set of delay elements within a programmable delay circuit. The programmable delay circuit optionally includes a tap point multiplexer for varying the number of delay elements in the delay path, to provide greater range of frequency multiple and faster lock.

Adjustable clock multiplier and method

A circuit and method are provided wherein a receiver receives an input train of pulses. The circuit includes a delay-locked-loop coupled to an output of the receiver. The delay-locked-loop includes a pulse generator responsive to received input train of pulses produced at the output of the receiver for producing first pulses in response to the leading edges of the received input train of pulses and second pulses in response to the trailing edges of received input train of pulses. The leading edge of the first pulse has the same edge type as the leading edge of the second pulse (i.e., the leading edge of the first pulse and the leading edge of the second pulse are either both rising edge types or both falling edges types). The first pulses and the second pulses are combined into a composite input signal comprising the first and second pulses with the leading edge of the first pulse maintaining the same edge type. The delay-locked-loop also includes a variable delay line fed by the composite input signal for producing a composite output train of pulses comprising both the first train of pulses and the second train of pulses after a selected time delay provided by the delay line. The delay-locked-loop is responsive to one of the first train of pulses and the second train of pulses in the composite output train of pulses for selecting the time delay of the variable delay line so as to produce the composite output train of pulses with a predetermined phase relationship to the input train of pulses.

Growing community of inventors

Mineville, NY, United States of America

Jason Edward Rotella