Sibercore Technologies, Inc.

Core Networks L.l.c.

Jason Edward Podaima

Radu Avramescu

G F Randall Gibson

Sanjay Gupta

Graham A Allan

Farhad Shafai

Randall Gibson

Kenneth J Schultz

Farhard Shafai

Garnet Fredrick Gibson

An invention is provided for lowLowpower searching in a CAMusingusessample words to save power in the compare lines.The inventionA methodincludes comparing a sample section of stored data to a corresponding sample section of search data on a plurality of rows in the CAM. If a sample section of the stored data on any row of the plurality of rows is equivalent to the corresponding sample section of the search data, a remaining section of search data is allowed to propagate to the local compare lines coupled to the remaining section of the stored data of each row. However, if the sample section of the stored data is different from the corresponding sample section of the search data, the local compare lines coupled to the remaining section of the stored data on each row are latched.

System and method for low power searching in content addressable memories using sampling search words to save power in compare lines

A content addressable memory (CAM) is provided that can perform wide word searches. At least one CAM memory core having a plurality of bit pattern entry rows is included in the CAM. In addition, search logic is included that, is capable searching particular rows during each cycle. The search logic is also capable of allowing match line results of unsearched rows to remain unchanged during a cycle. The CAM further includes a serial AND array in communication with the bit pattern entry rows, wherein the serial AND array is capable of computing a match result for wide word entries that span multiple bit pattern entry rows. In one aspect, a match line enable signal is provided to the serial AND array, which facilitates computation of the match result.

Word search in content addressable memory

Wide word search using serial match line computation in content addressable memory

An invention is provided for low power searching in a CAM using sample words to save power in the compare lines. The invention includes comparing a sample section of stored data to a corresponding sample section of search data on a plurality of rows in the CAM. If a sample section of the stored data on any row of the plurality of rows is equivalent to the corresponding sample section of the search data, a remaining section of search data is allowed to propagate to the local compare lines coupled to the remaining section of the stored data of each row. However, if the sample section of the stored data is different from the corresponding sample section of the search data, the local compare lines coupled to the remaining section of the stored data on each row are latched.

System and method for low power searching in content addressable memories using sample search words to save power in compare lines

An invention is disclosed for a content addressable memory (CAM) with a block select for power management. The CAM includes a plurality of memory blocks for storing data addressable within the CAM, and a search port in communication with the plurality of memory blocks. The search port is capable of facilitating search operations using the memory blocks. Also included in the CAM is a block select bus capable of selecting at least one specific memory block from the plurality of memory blocks. By using the block select bus, the search operations are performed using only the selected memory blocks. Similar to search operations, the block select signal or a similar signal can also be used to select specific memory blocks, wherein maintenance operations are performed using only the selected memory blocks.

Content addressable memory with block select for power management

A priority resolver for use in a CAM circuit priority encoder is provided. The priority resolver includes one or more priority resolver sub-units. Each priority resolver sub-unit includes an local hit (pehit) generation circuitry. The local hit (pehit) generation circuitry is configured to generate pehit data. Also provided as part of a priority resolver sub-unit is a resolve processing circuit that is coupled to the local hit (pehit) generation circuitry. The resolve processing circuit is configured to receive the pehit data and an enable signal. Preferably, the resolve processing circuit includes input gating circuitry. An output differentiator and gating circuit is further provided as part of the priority resolver sub-unit and is configured to receive an output of the resolve processing circuit. In this embodiment, the priority resolver sub-unit is implemented in one or more stages of the priority resolver, and each stage is configured to include one or more priority resolver sub-units.

Priority encoder with multiple match function for content addressable memories and methods for implementing the same

The present invention provides a CAM circuit having a redundant array and method for implementing the same. The circuit includes a first CAM array, a redundant CAM array, one or more storage devices, a first encoder, and a redundant encoder. The first CAM array stores data and has a plurality of first entries. Each first entry has a plurality of first memory cells, wherein any first entry that includes one or more defective first memory cells is defective. The redundant CAM array has one or more redundant entries of redundant memory cells. Each of the one or more redundant entries has a redundant address and is associated with a defective first entry, wherein each redundant entry is configured store data for the associated first entry. The one or more storage devices associate each of the defective first entries with a redundant entry. The first encoder outputs a first search result from the first CAM array while the redundant encoder outputs a redundant search result from the redundant CAM array according to a specified algorithm.

Content address memory circuit with redundant array and method for implementing the same

Binary and ternary content addressable memory (CAM) cells are disclosed, which permit the construction of high-performance, large-capacity CAM arrays. The CAM cells have a reduced match line power dissipation, and a reduced compare line loading that is data independent, and full swing comparator output. Match line power dissipation is limited by means of a NAND chain match line. Loading on compare lines is limited by connecting compare lines to the gate terminals of the CAM cell comparator. Local precharge devices at the output of the comparator provide full swing compare logic levels for faster matching. The same precharge devices also serve as an active reset for the comparator. Comparator circuits for ternary CAM cells further employ disable means, which makes the comparison operation conditional on the value stored in the mask memory element. The use of disable means allows the mask and data to be stored separately in a non-encoded form. As a result, mask and data information may be read and written independently of one another.

Growing community of inventors

Kanata, Canada

Jason Edward Podaima