International Business Machines Corporation

Jsr Corporation

Jrs Corporation

Globalfoundries Inc.

Jason E Cummings

Mahadevaiyer Krishnan

Michael F Lofaro

Tomohisa Konno

Tatsuya Yamanaka

Dinesh Kumar Penigalapati

Dinesh R Koli

Masahiro Noda

Leslie Charns

Jakub W Nalaskowski

Lukasz J Hupka

William R Tonti

Toshiharu Furukawa

Hemanth Jagannathan

Robert Russell Robison

Sanjay C Mehta

Balasubramanian S Haran

David V Horak

Jed Hickory Rankin

Wagdi William Abadeer

Kiran V Chatty

Lisa F Edge

Kangguo Cheng

Takashi Ando

Robert J Gauthier, Jr

Josephine B Chang

Michael A Guillorn

John Michael Cotte

Nathaniel C Berliner

Lilian Kamal, Legal Representative

Robert J Gauthier

Jed H Rankin, Jr

Various aspects include extremely thin semiconductor-on-insulator (ETSOI) layers. In one embodiment, an ETSOI layer includes a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; at least one recess located within the distinct SOI regions; and an oxide cap over the at least one recess.

Extremely thin semiconductor-on-insulator (ETSOI) layer

An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.

Creating extremely thin semiconductor-on-insulator (ETSOI) having substantially uniform thickness

A shallow trench isolation region is provided in which void formation is substantially or totally eliminated therefrom. The shallow trench isolation mitigates active shorts between two active regions of a semiconductor substrate. The shallow trench isolation region includes a bilayer liner which is present on sidewalls and a bottom wall of a trench that is formed in a semiconductor substrate. The bilayer liner of the present disclosure includes, from bottom to top, a shallow trench isolation liner, e.g., a semiconductor oxide and/or nitride, and a high k liner, e.g., a dielectric material having a dielectric constant that is greater than silicon oxide.

Method and structure for shallow trench isolation to mitigate active shorts

A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 &#x212b;-100 &#x212b;) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfO, AlO, ZrO, HfZrO, and HfSiO. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

Method to improve wet etch budget in FEOL integration

Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.

Chemical mechanical planarization with overburden mask

A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.

Chemical mechanical planarization processes for fabrication of FinFET devices

Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.

Fabrication of replacement metal gate devices

A polishing method includes polishing, in a first polish, a wafer to remove overburden and planarize a top layer leaving a portion remaining on an underlying layer. A second polishing step includes two phases. In a first phase, the top layer is removed and the underlying layer is exposed, with a top layer to underlying layer selectivity of between about 1:1 to about 2:1 to provide a planar topography. In a second phase, residual portions of the top layer are removed from a top of the underlying layer to ensure complete exposure of an underlying layer surface.

Shallow trench isolation chemical mechanical planarization

Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.

Forming an extremely thin semiconductor-on-insulator (ETSOI) layer

Growing community of inventors

Albany, NY, United States of America

Jason E Cummings