International Business Machines Corporation

University of Illinois

Jason David Morsey

Steven Eugene Washburn

Barry Jay Rubin

Patrick M Williams

Peter Feldmann

Tsz-mei Ko

Weng C Chew

Yuan Liu

Thomas G Mitchell

Lijun Jiang

Kerim Kalafala

James Douglas Warnock

Jeffrey G Hemmett

Michael H Wood

Debjit Sinha

Peter Claude Elmendorf

Chaitanya Ravindra Peddawad

Mao-kun Li

Mao-Kin Li

The efficiency of electronic design automation is increased by building, as an electronic data structure, a timing graph characterizing a putative integrated circuit design; identifying at least one of an edge and a node in the timing graph that requires canonical timing adjustment; and electronically calculating a deterministic timing adjustment for each of a plurality of corner cases. Based on the calculated deterministic timing adjustment for each of the plurality of corner cases, the canonical timing adjustment is determined for the at least one of an edge and a node; the canonical timing adjustment is applied to the timing graph; and the timing graph is updated based on the application of the canonical timing adjustment.

Efficient projection based adjustment evaluation in static timing analysis of integrated circuits

A system and method to perform an integrated circuit design involves selecting a net among a plurality of nets of the integrated circuit design as a victim net. Each net connects a pair of nodes of the integrated circuit design and each node represents a logic element of the integrated circuit design. The method also includes determining aggressor nets among the plurality of nets for the victim net and determining a corresponding weight value for each of the aggressor nets and, for each of the aggressor nets, multiplying the coupled noise originating from the aggressor net with the corresponding weight value to obtain a weighted coupled noise value. A cumulative coupled noise value is obtained for the victim net as a sum of the weighted coupled noise values associated with each of the aggressor nets. A result of the integrated circuit design is provided for fabrication into an integrated circuit.

Pessimism reduction in cross-talk noise determination used in integrated circuit design

A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim circuit sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.

Pessimism reduction in hierarchical blockage aggressors using estimated resistor and capacitor values

Coupled noise from at least one out-of-context aggressor net of an integrated circuit design is computed for an out-of-context victim net. The nets are out-of-context with respect to a hierarchical noise analysis of the integrated circuit design. At least one of the nets is a continuation of a path which extends to at least one in-context portion of the integrated circuit design. An aggressor signal timing window is derived for the at least one out-of-context aggressor net; a victim signal timing window is derived for the out-of-context victim net; and a timing window and noise analysis is completed with the aggressor signal timing window and the victim signal timing window. The aggressor window is derived as a function of required arrival time of the at least one out-of-context aggressor net and/or the victim window is derived as a function of required arrival time of the out-of-context victim net.

Using required arrival time constraints for coupled noise analysis and noise aware timing analysis of out-of-context (OOC) hierarchical entities

A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC design, generating a blockage circuit section that represents a blockage aggressor circuit in the IC design, using the copied one or more victim circuit sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.

A system to design an integrated circuit and a method of fabricating an integrated circuit include performing a design change for a net among a plurality of nets of the integrated circuit. An extraction is performed for the net and includes re-computing values for a resistor-capacitor (RC) circuit representation of the net. Re-computed values resulting from the re-computing and a timestamp of the extraction are recorded. A capacitance value of a capacitor coupling the net with a neighboring net in the RC circuit representation of the neighboring net is changed to be the capacitance value of the capacitor coupling the net with the neighboring net that was re-computed for the RC circuit representation of the net. Timing and noise parameters are for the net and the neighboring net are updated to updated timing and noise parameters, and timing analysis is performed based on the updated timing and noise parameters.

Approximation of resistor-capacitor circuit extraction for thread-safe design changes

A method for performing a signal integrity analysis on an integrated circuit (IC) that includes a plurality of scatterers by dividing the scatterers into subgroups using a nested Huygens' equivalence principle algorithm and solving a set of equations realized thereby with a reduced coupling matrix. The method includes decomposing the IC design into a plurality of small non-overlapping circuit sub-domains, wherein each of the sub-domains is formed as a small, enclosed region. Each sub-domain is analyzed independently of the other sub-domains using only electric fields to represent the interactions of each sub-domains with the other sub-domains as equivalent currents on equivalent surfaces of the plurality of sub-domains. Neighboring equivalent sub-domains are grouped together to form larger sub-domains using equivalent currents on equivalent surfaces to represent the interactions of the sub-domains. The steps of analyzing and grouping the sub-domains are repeated until the grouping approaches a box comprising the entire domain, and that the domain interactions between every sub-domain have been analyzed.

Huygens' box methodology for signal integrity analysis

This invention relates to computing numerical solutions of linear systems of equations, specifically to implementing preconditioning of the coefficient matrix of such a system. The preconditioning applies to any coefficient matrix, dense or sparse, based on the solutions of a physical problem of unknown functions, commonly referred to as basis or interpolation functions, where the basis function spans more then one mesh element. Examples of such linear systems can result from, as examples, an electromagnetic analysis of printed circuit boards or field scattering in radar applications, fluid mechanics and acoustics. A method and system to compute a preconditioner for a coefficient matrix A that is compatible with the linear system of equations that provides basis function support over at least two mesh elements. Coupling of the preconditioner between partitions of a portioned mesh representation is only through basis functions at the partition boundaries.

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Hopewell Junction, NY, United States of America

Jason David Morsey