National Instruments Corporation

Jason D Tongen

Jonathan W Hearn

Craig S Jones

Eric R Gardiner

Sundeep Chandhoke

Feng Jiang

Ryan C Croom

Daniel P Marcotte

System and method for determining and conveying connectivity of cabled computer peripherals to a user. Characteristic information regarding each of multiple devices connected to a computer system in a system hierarchy of a bus networked system may be stored, including a device hierarchy associated with each device that identifies respective hardware nodes included in the device, and one or more visual attributes of the device. Respective system positions may be automatically determined for at least some of the devices based on the device hierarchy. A respective point of reference of at least one device may be determined based on the characteristic information of one or more of the devices. The computer system may generate information that indicates the respective system position of the at least one device relative to the respective point of reference of the device, which is useable to visually identify the device in the bus networked system.

Automatically determining and indicating system positions of devices in a hierarchical bus networked system

A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.

Opaque bridge for peripheral component interconnect express bus systems

A mapping and correspondence may be established between a virtual topology and a physical topology of a PCIe subsystem, and a host may be presented with the virtual topology but not the actual physical topology. A semi transparent bridge may couple an upstream host to the PCIe subsystem that includes intermediary bridges and respective PCIe endpoints coupled downstream from the intermediary bridges. The intermediary bridges may be hidden from the host, while the respective PCIe endpoints may be visible to the host. A configuration block may provide to the upstream host, during a setup mode, first memory allocation information corresponding to the intermediary switches, responsive to the upstream host expecting second memory allocation information corresponding to the respective PCIe endpoints. The configuration block may then provide to the upstream host, during a runtime mode, the second memory allocation information, responsive to the upstream host expecting the second memory allocation information.

Hidden base address register programming in peripheral component interconnect express buses

Techniques for isochronous data transfer between different memory-mapped domains in a distributed system. A method includes configuring an isochronous engine with an isochronous period. The method further includes transferring data over a memory-mapped fabric from a first memory to a second memory during a specified portion of a cycle of the isochronous period. The first memory is comprised in a first device in a first memory-mapped domain of the memory-mapped fabric and the second memory is comprised in a second device in a second memory-mapped domain of the memory-mapped fabric. The method may further comprise translating one or more addresses related to the transferring. The memory-mapped fabric may be a PCI-Express fabric. The transferring may be performed by a DMA controller. A non-transparent bridge may separate the first and the second memory-mapped domains and may perform the translating.

Isochronous data transfer between memory-mapped domains of a memory-mapped fabric

A system and method for reserving resources of a host computer for use by an external device configured to be coupled to an expansion bus of the host computer are described. The host computer may be configured to execute device resource software that operates at a startup of the host computer to reserve one or more resources for the external device. The external device may not be available during the startup of the host computer, e.g., because the external device is not powered on or is not physically connected to the host computer. The device resource software may subsequently detect that the external device becomes available after the startup of the host computer. In response, the device resource software may enable the external device to use the one or more resources that were previously reserved at the startup of the host computer.

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Austin, TX, United States of America

Jason D Tongen