International Business Machines Corporation

Globalfoundries Inc.

Mentor Graphics Corporation

Inetrnational Business Machines Corporation

Jason D Hibbeler

Robert F Walker

Robert J Allen

Juergen Koehl

Kevin W McCullen

Rani Narayan

Jeanne P Bickford

Fook-Luen Heng

Daniel Nelson Maynard

Michael S Gray

William Robert Reohr

Phillip John Restle

Xin Yuan

Dureseti Chidambarrao

Gustavo Enrique Tellez

Markus Buehler

John Maxwell Cohn

James A Culp

Alan J Drake

Liang-Teck Pang

Thomas J Bucelot

Matthew Thomas Guzowski

Cam V Endicott

Michael G R Thomson

Robert Allen Groves

Paul S Chang

Anda C Mocuta

Stephen Larry Runyon

Praveen Elakkumanan

Yong I Kim

Edward J Nowak

Brent A Anderson

Terence B Hook

Kirk David Peterson

Dongbing Shao

Mervyn Y Tan

Paul H Bergeron

Zachary Henderson

Nicholas Palmer

Anthony K Stamper

Jed Hickory Rankin

David James Hathaway

Albert Manhee Chu

Evanthia Papadopoulou

Daria Rose Dooling

Ralph James Williams

William John Livingstone

Faye D Baker

Jeanne Paulette Spence Bickford

Sarah C Braasch

Veit Gernhoefer

Jhy-Chun Wang

Sarah C Prue

Steven Zebertavage

Xiaoyun K Wu

Lawrence Alfred Clevenger

Tak H Ning

Mark Charles Hakey

Lars W Liebmann

John Atkinson Fifield

Kenneth Parker Rodbell

Robert C Wong

Sani Richard Nassif

Richard Quimby Williams

Anthony Correale, Jr

Wayne Harvey Woods, Jr

James Spiros Nakos

Jeffrey G Hemmett

Ulrich Alfons Finkler

Gregory Scott Still

Rouwaida N Kanj

Ronald Dennis Rose

Leon Jacob Sigal

Christopher J Gonzalez

Larry Wissel

Richard L Rassel

Lewis William Dewey, Iii

Tina Jane Wagner

Kevin N Ogg

Henry A Bonges, Iii

Joshua D Friedrich

Cole E Zemke

Henry H K Tang

Mervyn Yee-Min Tan

Pieter J Woeltgens

Gie Lee

Theodore G Hoover, Jr

Stephen I Runyon

Bruce C Wheeler

Daniel Nelson Mayuard

Cheng A Feng

Judith K Ingles

A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.

Optimizing integrated circuit designs based on interactions between multiple integration design rules

Embodiments include methods, design layout optimization systems, and computer program products for optimizing design layout of integrated circuits. Aspects include receiving a design layout of an integrated circuit from a design layout tool module, identifying a critical pitch in the design layout received, searching design rules forming design arc limited by identified critical pitch from a set of design rules associated with the received design layout, extracting a process variation and one or more failure mechanisms of design layout based on critical pitch and rules forming design arc identified, performing layout based ground rule calculation based on the process variation and the one or more failure mechanisms extracted, determining whether wafer risks exist in the design layout, responsive to determining the wafer risks exist in the design layout, revising the design layout and performing additional layout based ground rule calculation after the revision, and otherwise, outputting an optimized design layout.

Integrated circuit design layout optimizer based on process variation and failure mechanism

Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.

Immunity to inline charging damage in circuit designs

A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device.

Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor

A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.

Tunable sector buffer for wide bandwidth resonant global clock distribution

Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.

Setting switch size and transition pattern in a resonant clock distribution system

A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.

Wide bandwidth resonant global clock distribution

Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Methods and system for analysis and management of parametric yield

Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.

Changing resonant clock modes

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Williston, VT, United States of America

Jason D Hibbeler