Synopsys, Inc.

Alcatel Canada Inc.

Jason Chung-Shih Chen

Dhiraj Goswami

Ngai Ngai William Hung

Albert D Heller

Na Xing

Aijun Hu

Paul M Ruffle

A design verification workstation contains both debug and constraint solver capabilities during simulation of a design under test. The design verification workstation is configured to allow the user to debug constraints, stop the constraint solver, navigate problems and variables, and make modifications on-the fly during the simulation to constraint information. Additionally, in some embodiments, the design verification workstation may allow a user to use a constraint solver to experiment if the modifications will lead to desired test stimulus. Since this debug process happens during simulation, users do not need to recompile the test case. Additionally, once a user is satisfied with the modifications made to the simulation, the modification could be saved for future usage.

Development and debug environment in a constrained random verification

A method and apparatus for load distribution across memory banks with constrained access is accomplished using a bank balancer that ensures that data to be buffered is evenly distributed throughout the various banks of the memory structure. The bank balancer maintains bank depth information relating to each of the banks. The bank balancer receives dequeue and enqueue information, where the dequeue information specifies read operations that will remove data from the various banks, and the enqueue information indicates that there is data to be written to the memory banks. The dequeue information constrains which banks may be utilized to enqueue received data. In order to determine to which banks to enqueue data, the bank balancer sorts the banks by their depth. The bank balancer then eliminates those banks which cannot be used for enqueue operations due to either the dequeue operations or other enqueue operations that have already been determined. Once a sorted list of eligible banks for enqueuing has been established, the bank balancer selects the bank storing the least amount of data which is eligible. The depth information for each bank is updated based on the enqueue and dequeue operations, and the bank balancer re-sorts the banks such that the changes in depth are taken into account in the following cell period.

Method and apparatus for load distribution across memory banks with constrained access

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Ottawa, Canada

Jason Chung-Shih Chen