Lattice Semiconductor Corporation

Jason Cheng

Satwant Singh

Ju Shen

Cyrus Y Tsui

Clement Lee

Om P Agrawal

Albert L Chan

Bradley Felton

Paul R Bonwick

Andrew Armitage

Albert Chen

A programmable logic device includes a plurality of logic blocks organized into a cluster. Each logic block may be configured into a logic mode and a memory mode. The logic blocks are arranged into at least one cluster, each cluster having a data bus configured to provide data words to logic blocks within its cluster.

Programmable logic device with flexible memory allocation and routing

A programmable device with logic blocks is configured to cascade product terms from one logic block to another to increase the logical input width of the product terms. Each logic block may produce a plurality of product terms based upon the selection of inputs from a routing structure. Logic blocks configured to receive cascaded product terms includes a plurality of AND gates corresponding to the plurality of product terms.

Programmable logic device with enhanced wide input product term cascading

The fuse points within a programmable AND array may be programmed with configuration signals to select for logical signals to form product term outputs in a logic mode. In a switch mode, a subset of these fuse points may be programmed with dynamically-created operating signals to form a cross point switch matrix.

Dynamic cross point switch with shadow memory architecture

A programmable device and method with generic logic blocks. Each generic logic block is configurable to perform product term logic functions and memory functions, such as RAM, dual-port RAM, ROM, CAM, FIFO and switch.

Device and method with generic logic blocks

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Fremont, CA, United States of America

Jason Cheng