Holtek Microelectronics Inc.

Holtek Semiconductor Corp.

Industrial Technology Research Institute

Ambit Microsystems Corporation

Jason Chen

Paul Chen

George Chang

Henry Fan

Yi Lin

Kuo-Hsiang Chen

Kuo Cheng Yu

I Liang Fang

Kuo-Cheng Yu

Chun-Ku Lin

Peter Liu

Bao-Shiang Sun

In the present invention, a temperature compensation circuit is provided. The temperature compensation circuit includes a first oscillator for providing a first clock signal, a timer electrically connected to the first oscillator for clocking a specific time period, a voltage regulator for generating a constant voltage, a second oscillator electrically connected to the voltage regulator for providing a second clock signal, and a counter electrically connected to the second oscillator for counting within the specific time period based on the second clock signal so as to obtain a counting value, and thereby a frequency of the second oscillator is obtained for the temperature compensation.

Circuit and method for temperature compensation

A back lighting source module for a liquid crystal display comprises a pulse width modulation (PWM) controller for providing a pulse width signal to control output current of a lighting element. A half bridge converter includes two power transistors connected in series. An output is formed in a middle between the two power transistors. The output is controllable by the signal from the PWM controller to perform alternating opening and closing. A resonance circuit generates a sine-wave voltage to empower the lighting element. A feedback circuit includes a resistor. When a load varies, a voltage signal generated between two ends of the resistor of the feedback circuit timely changes a conductive time of the power transistors of the half bridge converter to complete regulation of current passing through the lighting element.

Back lighting source module for liquid crystal display

An integrated circuit is disclosed which includes a start test mode circuit for generating a test mode start-up signal to cause the integrated circuit to enter a test mode, and an automatic reset circuit responsive to the test mode start-up signal for preventing the integrated circuit from erroneously entering a test mode during normal operation.

Apparatus within an integrated circuit for preventing the integrated circuit from erroneously entering a test mode operation

A test method for charge redistribution type digital-to-analog and analog-to-digital converters by utilizing the special characteristics of a DAC or ADC such that the accuracy and linearity of the converted signal is only determined by the internal capacitance ratios of the converter, and that the accuracy and linearity are not related to the test reference voltage, the test voltage and the noise signal of the test machine. The test method utilizes a principle of capacitance comparison to directly compare the capacitance ratios in a converter in order to determine the accuracy and linearity of the converted signal. The present invention method enables an effective reduction in the test time and test steps required and an increase in the test efficiency.

Method for testing charge redistribution type digital-to-analog and

A voltage detector circuit for instantaneously detecting abnormal voltages in a micro controller includes a voltage detection circuit connected between the power supply and reset voltage ends of an internal circuit of the micro controller so as to instantaneously detect changes in the power supply, without the time delay associated with the external low pass filter that supplies the reset voltage. The detecting circuit is a logic 'NOT' gate which has a power supply connecting end connected to a reset voltage end of the internal circuit, an input end connected to the power supply end of the internal circuit, and an output end connected to a cooperating input end of the latch circuit, so that the latch circuit latches a signal output by the voltage detector whenever an abnormal power supply voltage is detected, and outputs a flag signal to the micro controller to effect an instantaneous reset of the micro controller. The latch may be a flip-flop, in which case one of the flip-flop inputs is connected to the voltage detector output and the other input may be connected together with the flip-flop power supply input to the reset voltage, the flip-flop providing two outputs, one of which may be connected to the micro controller reset pin, and the other of which may be connected to an interrupt or other indicator device.

Means for instantaneously detecting abnormal voltage in a micro

A high speed division method and apparatus that does not require the use of dividers are provided. The method and apparatus utilize a binary shift-add technique to simplify a divisional computation process and to enable computational error to be contained in a predetermined range, and to obtain a higher computing speed. The apparatus includes a divisor left-shift apparatus for inputting a divisor and to left-shift the divisor, a dividend left-shift apparatus for inputting a dividend and to left-shift the dividend, a left-shift controller for controlling the left-shift motion of the divisor, a quotient right-shift apparatus for inputting the indexes from a division table and then right-shift the quotient. The apparatus utilizes left-shift or right-shift to achieve a multiplication or division by 2.

Method and apparatus for high speed division

A data shift control circuit for a shift register in response to a logic operation command code is disclosed. The shift register includes a first register and a second register and the logic operation command code includes a first portion and a second portion. The circuit includes a first decoder for decoding the first portion to transmit a move signal; a second decoder for decoding the second portion to transmit a control signal; a control signal channel, electrically connected to the first register and the second register, for allowing the first register and the second register to receive the control signal and for allowing the shift register to execute a first action; and a move signal channel, electrically connected to all registers of the shift register for allowing the all registers to receive the move signal and for allowing the move register to execute a second action.

Data shift control circuit

A flag setting circuit for a microcontroller, which can be set with a HALT mode flag and a watchdog timer overflow flag by using a system power-on signal, an external reset signal, a watchdog timer overflow signal inside the microcontroller, a clear instruction for watchdog timer, a HALT mode instruction, and a wake-up signal. The setting circuit for the watchdog timer overflow flag includes a reset signal generator, a watchdog timer, a clear signal generator, a flag clear circuit, and a register circuit. The setting circuit for the HALT mode flag includes a HALT mode discerning circuit, a flag clear circuit, and a register circuit. The frequency source of the watchdog timer is provided by means of a frequency from the system oscillator divided with four, or by using a frequency of RC oscillator built in the system. Under the HALT mode, the RC oscillator is selected. By means of the HALT mode flag and the watchdog timer overflow flag, the operation condition of the system hardware can be discerned.

Flag setting circuit for microcontroller

A method of compressing an integer multiplication table including the steps of first eliminating one of the two symmetrical and identical sections in the table, eliminating the products of 0 multiplier and 0 multiplicand, moving the product of the multiplier having an index of n into the location of index (n-1) for the multiplier, using one-half of the number of the largest multiplier as the largest multiplier index for the compressed multiplication table, moving into the non-continuous memory space of the compressed multiplication table by a page-filling method the product of the largest multiplier index value that is larger than the compressed multiplication table such that the multiplication table after compression can be stored on the same page.

Method and apparatus for compression of integer multiplication table

A binary multiplication method utilizing a combined table lookup and long multiplication to simplify the multiplication procedure, to improve the computational speed, and to save half of the memory space normally required. The method is executed by first moving the least significant bit (LSB) of the multiplier to another memory device before the start of the computation and then using the shortened multiplier in the multiplication operation since the multiplier is reduced by one bit, the memory space required for the multiplication table is reduced by half. The method does not require the use of a multiplying device and only needs small memory space. The manufacturing cost of a microprocessor can be reduced accordingly.

Method and apparatus for integer multiplication

A method and apparatus for determining the degree of membership in a fuzzy inference by using a subtractor and a divider without the need for a complicated multiplication, division circuit or software that is normally required in a conventional method. A fuzzy inference database for the degree of membership is first established in a microprocessor by a fuzzy inference method, the membership function in the fuzzy database has a range between 0 to 1 at full scale for the degree of membership function. When the microprocessor detects an input data, a slope distance ratio and the corresponding coordinates are determined and compared using the input data and the fuzzy database established in the microprocessor. The ratio determined by the greatly simplified method is the degree of membership function.

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Ilan, Taiwan

Jason Chen