Intel Corporation

Jason C Stinson

Alper Ilkbahar

David N Harris

James Nadir

Sunny C Huang

Mathew B Nazareth

Ching-Hua Chu

Erik A De La Iglesia

Edwin R Lilya

An apparatus includes a test circuit, a first counter and a second counter. The test circuit is fabricated on a semiconductor substrate to generate an oscillating signal. The oscillating signal has a frequency that is dependent on at least in part a parameter of a process used to fabricate the test circuit. The first counter measures a time interval, and the second counter is coupled to the first counter to count a number of periods of the oscillating signal during the time interval.

Process parameter extraction

A circuit to vary a frequency of an input clock is disclosed. The circuit includes a delay generator to generate at least two delayed clocks from the input clock and a select circuit coupled to receive the at least two delayed clocks and provide an output clock from one of the at least two delayed clocks. The select circuit switches the output clock from the one of the at least two delayed clocks to the other of the at least two delayed clocks on a first edge.

Method and apparatus for varying a clock frequency on a phase by phase

An opportunistic time-borrowing domino logic includes a domino pipeline having a plurality of logic gates coupled in series and controlled by first, second, third and fourth clock signals. The first domino gate in a half-cycle is clocked by either the first or the second clock signals, wherein the last domino gate in a half-cycle is clocked by either the third or the fourth clock cycles. The second clock signal is an inverse of the first clock signal, and the third and fourth clock signals have local delayed clock phases in which the falling edges of the third and fourth clock signals are delayed relative to the falling edges of the respective first and second clock signals. In a first half-cycle, a first type of domino gate is controlled by the first clock signal, with subsequent domino gates of the same type being controlled by the third clock signal. Odd-numbered half-cycles begin with a domino gate of the second type controlled by the second clock signal, followed by domino gates of the first type controlled by the fourth clock signal.

Opportunistic time-borrowing domino logic

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Mountain View, CA, United States of America

Jason C Stinson