Intel Corporation

Jason B Akers

Sanjeev N Trika

Knut Stener Grimsrud

Robert J Royer, Jr

Richard Paul Mangold

Shankar Natarajan

Suresh Nagarajan

Sriram Natarajan

Chace Clark

Embodiments are directed towards apparatuses, methods, and systems associated with a storage reclamation manager that generates a command to reclaim storage locations to assist in management of a storage capacity of a primary storage device. In embodiments, the command is a trim command to inform the storage device of storage locations including invalid data. In embodiments, the command is generated during performance of operations associated with a write-back operation where a cache coupled with the processor stores a first portion of data and the primary storage device stores a corresponding second portion of data. In embodiments, the command is generated during or after a write-back operation of a third portion of data into the cache device. In embodiments, the command assists in reclamation of storage locations in which the second portion of data is stored, to assist in management of a storage capacity of the primary storage device. Additional embodiments may be described and claimed.

Apparatus, systems, and methods to reclaim storage associated with cached data

Systems, apparatuses and methods may provide for technology that writes a block of data addressed within a host managed cache region into a set of multi-level non-volatile memory (NVM) cells organized into a dynamic single level cell buffer region, that writes a block of data addressed outside the host managed cache region into the set of multi-level NVM cells organized into a static single level cell buffer region, and automatically writes the contents of the static single level cell buffer region into the dynamic multi-level NVM media region. The host manage cache region comprises a set of dynamic single level NVM cells within the dynamic multi-level NVM media region, and the multi-level NVM cells are to be dynamically convertible into and from single NVM cells.

Host managed solid state drivecaching using dynamic write acceleration

Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.

Architectures and techniques for providing low-power storage mechanisms

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Hillsboro, OR, United States of America

Jason B Akers