Ampere Computing LLC

Jason Anthony Bessette

Sean Philip Mirkes

Jonathan Christopher Perry

Jacob Daniel Morgan

John Saint Tran

Aspects disclosed include hardware micro-fused memory (e.g., load and store) operations. In one aspect, a hardware micro-fused memory operation is a single atomic memory operation performed using a plurality of data register operands, for example a load pair or store pair operation. The load pair or store pair operation is treated as two separate operations for purposes of renaming, but is scheduled as a single micro-operation having two data register operands. The load or store pair operation is then performed atomically.

Hardware micro-fused memory operations

Instruction scheduling in a processor using operation source parent tracking. A source parent is a producer instruction whose execution generates a produced value consumed by a consumer instruction. The processor is configured to track identifying operation source parent information for instructions processed in a pipeline and providing such operation source parent information to a scheduling circuit along with the associated consumer instruction. The scheduling circuit is configured to perform instruction scheduling using operation source parent tracking on received instruction(s) to be scheduled for execution. The processor is configured to compare sources and destinations for each of the instructions to be scheduled based on the operation source parent information to determine instructions ready for scheduling for execution. Given availability of the operation source parent information for instructions to be scheduled, the processor can perform a reduced number of comparisons of the sources and destinations for instructions to be scheduled.

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Santa Clara, CA, United States of America

Jason Anthony Bessette