International Business Machines Corporation

North Carolina State University

International Business Machines Corpation

Jason Alan Cox

Eric Francis Robinson

Lydia Mai Do

Mark J Wolski

Robert John Dorsey

Thuong Quang Truong

Hien Le

Richard Nicholas

Kevin C K Lin

Brian Robert Mestan

Brian Michael Rogers

Kimberly Marie Fernsler

Michael Lance Karm

Kevin C Lin

M V V Anil Krishna

Jana Helton Jenkins

Kerry Bernstein

Pamela Ann Nesbitt

William Gabriel Pagan

Lisa A Seacat

John F Muth

Omer Heymann

Edward R Grant

Robert J Bucki

Praveen Karandikar

Jagreet S Atwal

Joseph S Barnes

Nadav Levison

Keith A DeWeese

Kevin Chih Kang Lin

John Steven Cottle

Brian Ellery Dessent

Filtering snoop traffic in a multiprocessor computing system, each processor in the multiprocessor computing system coupled to a high level cache and a low level cache, the including: receiving a snoop message that identifies an address in shared memory targeted by a write operation; identifying a set in the high level cache that maps to the address in shared memory; determining whether the high level cache includes an entry associated with the address in shared memory; responsive to determining that the high level cache does not include an entry corresponding to the address in shared memory: determining whether the set in the high level cache has been bypassed by an entry in the low level cache; and responsive to determining that the set in the high level cache has not been bypassed by an entry in the low level cache, discarding the snoop message.

Filtering snoop traffic in a multiprocessor computing system

Ensuring forward progress of token-required cache operations in a shared cache, including: snooping an instruction to execute a token-required cache operation; determining if a snoop machine is available and if the snoop machine is set to a reservation state; if the snoop machine is available and the snoop machine is in the reservation state, determining whether the instruction to execute the token-required cache operation owns a token or is a joint instruction; if the instruction is a joint instruction, instructing the operation to retry; if the instruction to execute the token-required cache operation owns a token, dispatching a cache controller; determining whether all required cache controllers of relevant compute nodes are available to execute the instruction; executing the instruction if the required cache controllers are available otherwise not executing the instruction.

Ensuring forward progress of token-required cache operations in a shared cache

An intelligent prediction approach populates and depopulates multiple applications at the system level across applications. The detection and management of user behavior patterns anticipates the user's next request and relates dynamically to user behavior and where that user behavior changes to adjust so as to more accurately set forth a desired result for a user of the present invention.

Dynamically manage applications on a processing system

Acquiring access to a token controlled system resource, including: receiving, by a token broker, a command that requires access to the token controlled system resource, where the token broker is automated computing machinery for acquiring tokens and distributing the command to the token controlled system resource for execution; identifying, by the token broker, a first need state, the first need state indicating that the token broker requires access to the token controlled system resource to which the token broker does not possess a token; requesting, by the token broker, a configurable number of tokens to gain access to the token controlled system resource, without dispatching an operation handler for executing the command until at least one token is acquired; assigning, by the token broker, an acquired token to the operation handler; and dispatching, by the token broker, the operation handler and its assigned token for executing the command.

Acquiring access to a token controlled system resource

An Activity Access Control (AAC) utility controls access to applications and devices by allowing an administrator to set terms of use/access regarding a applications and/or devices for a group of users, whose activity are monitored. The AAC utility also enables administrator and user access to a compromise facility via a centralized access point to establish or request changes to the terms of use/access. The AAC utility allows the administrator to dynamically update information and set terms based on real-time information collected during activity monitoring. Dynamic updates may also occur based on the monitored user's request, the priority of the requesting user(s), historical data, occurrence of a special event, completion of other internal or/external tasks, and/or pre-set limitations or thresholds. In addition, the AAC utility facilitates the real-time display or publishing of the terms of use, status information, and statistical information to users and the administrator.

System for online compromise tool

An L2 cache, method and computer program product for transferring an inbound bus operation to a processor side handling machine. The method includes a bus operation handling machine accepting the inbound bus operation received over a system interconnect, the bus operation handling machine identifying a demand operation of the processor side handling machine that will complete the bus operation, the bus operation handling machine sending the identified demand operation to the processor side handling machine, and the processor side handling machine performing the identified demand operation.

Transfer of bus-based operations to demand-side machines

Methods, apparatuses, and computer program products are disclosed for cache management. Embodiments include receiving, by a cache controller, a request to insert a new cache line into a cache; determining, by the cache controller, whether the new cache line is associated with a forced injection; in response to determining that the new cache line is associated with a forced injection, accepting, by the cache controller, the insertion of the new cache line into the cache; and in response to determining that the new cache line is not associated with a forced injection, determining, by the cache controller, whether to accept the insertion of the new cache line based on a comparison of an address of the new cache line to a predefined range of addresses.

Managing unforced injections of cache lines into a cache utilizing predetermined address ranges

One embodiment provides a cached memory system including a memory cache and a plurality of read-claim (RC) machines configured for performing read and write operations dispatched from a processor. According to control logic provided with the cached memory system, a hazard is detected between first and second read or write operations being handled by first and second RC machines. The second RC machine is suspended and a subset of the address bits of the second operation at specific bit positions are recorded. The subset of address bits of the first operation at the specific bit positions are broadcast in response to the first operation being completed. The second operation is then re-requested.

Address-based hazard resolution for managing read/write operations in a memory cache

A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.

Multi-wafer 3D CAM cell

A method for maintaining cache coherency operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache, and each PU coupled to at least another one of the plurality of PUs. A first PU receives a first data block for storage in a first cache of the first PU. The first PU stores the first data block in the first cache. The first PU assigns a first coherency state and a first tag to the first data block, wherein the first coherency state is one of a plurality of coherency states that indicate whether the first PU has accessed the first data block. The plurality of coherency states further indicate whether, in the event the first PU has not accessed the first data block, the first PU received the first data block from a neighboring PU.

System and method for cache coherency in a multiprocessor system

A method and system in accordance with the present invention provides an intelligent prediction approach for populating and depopulating multiple applications at the system level across applications. The detection and management of user behavior patterns to anticipate the user's next request is provided. Further the present invention is to account for a situation to relate dynamically to user behavior and where that user behavior changes to adjust so as to more accurately set forth a desired result for a user of the present invention. The present invention in various implementations provides an intelligent prediction scheme for populating and depopulating multiple applications at the system level across a diversity of applications.

System and method to dynamically manage applications on a processing system

Methods and apparatuses are disclosed for direct access to cache memory. Embodiments include receiving, by a direct access manager that is coupled to a cache controller for a cache memory, a region scope zero command describing a region scope zero operation to be performed on the cache memory; in response to receiving the region scope zero command, generating a direct memory access region scope zero command, the direct memory access region scope zero command having an operation code and an identification of the physical addresses of the cache memory on which the operation is to be performed; sending the direct memory access region scope zero command to the cache controller for the cache memory; and performing, by the cache controller, the direct memory access region scope zero operation in dependence upon the operation code and the identification of the physical addresses of the cache memory.

Direct access to cache memory

A method and system for utilizing a game console and an input device is disclosed. The method and system comprise mapping commands to system directives of the game console and generating an input signal having predefined characteristics corresponding to the input device being utilized to engage the system directives. The method and system include performing system functions using an input controller associated with the input device after the system directives are engaged.

Game console control to initiate system directives

A method for managing data operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache comprising a plurality of cache lines, each cache line having one of a plurality of coherency states, and each PU coupled to at least another one of the plurality of PUs. A first PU selects a castout cache line of a plurality of cache lines in a first cache of the first PU to be castout of the first cache. The first PU sends a request to a second PU, wherein the second PU is a neighboring PU of the first PU, and the request comprises a first address and first coherency state of the selected castout cache line. The second PU determines whether the first address matches an address of any cache line in the second PU. The second PU sends a response to the first PU based on a coherency state of each of a plurality of cache lines in the second cache and whether there is an address hit. The first PU determines whether to transmit the castout cache line to the second PU based on the response. And, in the event the first PU determines to transmit the castout cache line to the second PU, the first PU transmits the castout cache line to the second PU.

Growing community of inventors

Raleigh, NC, United States of America

Jason Alan Cox