Semiconductor Insights Inc.

Techinsights Inc.

Jason Abt

Vyacheslav L Zavadsky

Edward Keyes

Val Gont

Stephen Begg

Christopher Pawlowicz

Heinz Josef Nentwich

Ian Jones

Robert K Foster

Mohammed Ouali

Larry Lam

Alexei Ioudovski

Mark Braverman

Elmehdi Aitnouri

Vladimir Martincevic

Thomas Kapler

Heinz Nentwich

There is provided a method, system and computer program product to delayer a layer of a sample, the layer comprising one or more materials, in an ion beam mill by adjusting one or more operating parameters of the ion beam mill and selectively removing each of the one or more materials at their respective predetermined rates. There is also provided a method and system for obtaining rate of removal of a material from a sample in an ion beam mill.

Method and system for ion beam delayering of a sample and control thereof

A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and then deleted. Dummy features may be detected by selecting a representative dummy feature, using it as a reference pattern or polygon and comparing it to features in the source data structure. The step of comparing the selected reference to the comprises selecting a cut-off correlation threshold value, and computing the correlation coefficients between the reference and the feature. Features are selectively removed based on a comparison between their correlation coefficients and the selected cut-off correlation threshold value. This threshold value may require updating to remove all dummy features in the source data structure. When different shaped dummy features in the same data structure are encountered, a further reference feature may be selected and the process repeated.

Method and apparatus for removing dummy features from a data structure

The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

Method of design analysis of existing integrated circuits

The present invention provides a method and apparatus for reducing uneven brightness in an image from a particle based image system. This uneven brightness is most often seen as regions of shadow, but may also be seen as regions of over brightness. In cases where the uneven brightness is in the form of shadowing, the method corrects for the shadowy regions by first identifying the area of shadow, obtaining brightness information from a region near the shadow, where the brightness is optimal, applying statistical methods to determine the measured brightness as a regression function of the optimal brightness, and number and proximity of shadowy objects, then correcting the shadow area brightness by calculating the inverse of the function of the shadow brightness. With this method, the brightness within the shadowy or over brightness regions are corrected to appear at a substantially similar level of brightness as the region of optimal brightness in the image.

Method and apparatus for removing uneven brightness in an image

A method of registering and vertically aligning multiply-layered images into a mosaic is described. The method comprises performing an iterative process of vertical alignment of layers into a mosaic using a series of defined alignment correspondence pairs and global registration of images in a layer using a series of defined registration correspondence points and then redefining the identified alignment correspondence pairs and/or registration correspondence points until a satisfactory result is obtained. Optionally, an initial global registration of each layer could be performed initially before commencing the alignment process. The quality of the result could be determined using a least squares error minimization or other technique.

Method of registering and aligning multiple images

The method and apparatus in accordance with the present invention determines the locations of incorrectly connected polygons in a polygon representation of an integrated circuit layout. These incorrectly connected polygons result in short circuits, which often occur for major signal busses such as power and ground. It can be time-consuming to determine the exact location of the short. The invention includes the step of tessellating the polygon representation, including each conductive layer, into predetermined shapes such as triangles or trapezoids. Each of the triangles or trapezoids is then translated into a node for the development of a nodal network where nodes are connected directly to one another to represent shapes having edges adjacent to other shape edges. The current capacity of each connection between adjacent nodes is then specified. Two nodes that are electrically connected to the incorrectly connected polygons are selected and used as parameters for a network flow analysis algorithm. This algorithm determines the areas of high density where high flow is dictated by the triangle or trapezoid having the lowest current capacity. The areas of high density are flagged as points where short circuits may exist. These flagged points may then be investigated to confirm whether they are short circuits.

Method and apparatus for locating short circuit faults in an integrated circuit layout

An editor in a computer system for editing an schematic having a number of pages. The editor may cut a selected portion of the schematic from any one of the schematic pages, paste the cut portion of the schematic onto any one of the schematic pages, and connect nets located on the same schematic page. The editor may search for objects such as signal labels and cells within the schematic netlist as well as other editing functions. Further a navigator is provided for interactively viewing netlist data from a high level schematic where the data includes schematic page numbers, cell names, nets, signal labels and segments. The project viewer software and project schematic netlist data may be contained in a computer-readable medium. The project viewer software controls output schematic images and enables a user to view, trace and search objects throughout the project netlist data.

Advanced schematic editor

A method and apparatus for extracting circuit design information from a pre-existing semiconductor integrated circuit (IC) or at least a portion thereof is described. It includes imaging at least a portion of two or more physical layers of the pre-existing IC to obtain stored electronic images of the physical IC layers, converting the stored electronic images of the physical IC layers to a vector format data, horizontally and vertically aligning the vector format data of the electronic stored images of the physical IC layers, and providing a multi-layer display of the aligned vector format data. A net-list or schematic is generated from the multi-layer display of the vector format data. The net-list and/or schematic may be generated as a number of individual pages by providing a template of circuit elements and placing a circuit element over a portion of the display corresponding to the circuit element. The template of circuit elements may include transistors, logic gates or complex circuit blocks. The vector format data may be altered to correct errors in the images or manipulated to correct the alignment of the images. In addition, the schematic may be traced to the image of the physical IC layer.

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Kanata, Canada

Jason Abt