Intel Corporation

Jasmin Ajanovic

David J Harriman

Mahesh U Wagh

Sridhar Muthrasanallur

Robert G Blankenship

Prashant Sethi

Debendra Das Sharma

Mark B Rosenbluth

Scott Dion Rodgers

Anil Vasudevan

Ilan Pardo

Ajay V Bhatt

James E Akiyama

Eran Tamari

Doron Shamia

Peter J Barry

Eliezer Weissmann

Ohad Falik

David M Lee

Blaise B Fanning

Abraham Mendelson

Kenneth C Creta

Avi Mendelson

Randy B Osborne

Dahmane Dahmani

Brian K Langendorf

Narendra S Khandekar

Abhishek Singhal

Robert N Murdoch

Avi (Abraham) Mendelson

Ravishankar Iyer

Gary A Solomon

Michael W Williams

Joseph A Bennett

Nilesh V Shah

Aaron T Spink

Lance E Hacking

Michael J Espig

George R Hayek

Zhen Fang

Serafin E Garcia

Eric R Wehage

Buck Gremel

Wayne Moore

Rajeev K Prasad

Ken Creta

Hong Jiang

David I Poisner

Robert J Greiner

Stephen S Pawlowski

Aditya Sreenivas

Jose Andy Vargas

Joseph H Salmon

Clifford D Hall

Radhakrishnan Venkataraman

James S Coke

Randolph L Campbell

Jeffrey L Rabe

C Brendan S Traw

Stuart E Sailer

Timothy M Dobbins

Kenneth C Holland

Michael J Muchnick

Jerry A Verseput

Steve Pawlowski

Patrick N Kearns

Ohad Fallk

Ellezer Weissmann

Avi (Arraham) Mendelson

Mike W Williams

A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages. The group of messages to include a message to unlock a logical device, a message to reset a logical device, a message to indicate a correctable error condition, a message to indicate an uncorrectable error condition, a message to indicate a fatal error condition, a message to report a bad request packet, a message to indicate power management and a message to emulate an interrupt signal.

Communicating a message request transaction to a logical device

A storage device is provided to maintain a count of flow control credits to be granted to a device in association with transactions over a channel to be implemented on a data link and control logic is provided to communicate, to the device, an indication of an amount of flow control credits for the device in association with a reset of the data link.

General input/output architecture, protocol and related methods to implement flow control

An enhanced general input/output communication architecture, protocol and related methods are presented.

In one embodiment, the present invention includes a fabric on a first semiconductor die to communicate with at least one agent on the die according to an on-chip protocol and a packetization layer coupled to the fabric to receive command and data information from the fabric on multiple links and to packetize the information into a packet for transmission from the die to another die via an in-package packetized link. Other embodiments are described and claimed.

Packetized interface for coupling agents

A storage device is provided to maintain a value of flow control credits allocated for a device on a channel and flow control logic is provided to receive a flow control signal over a link of an interconnect, the flow control signal indicating flow control credits allocated for the device on the channel. The flow control logic is further to update the value of flow control credits based on activity of the device on the channel.

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Atomic operations in PCI express

Transaction layer packet formatting

PCI express transaction descriptor

Transaction re-ordering

Growing community of inventors

Portland, OR, United States of America

Jasmin Ajanovic