Texas Instruments Corporation

Jasjot Singh Chadha

Lars Risbo

Ryan Erik Lind

Mohit Chawla

Sudhir Polarouthu

Sumit Dubey

Sahiti Priya C

Rejin Kanjavalappil Raveendranath

Shaik Asif Basha

Mukund Navada Kanyana

David Hernandez

Aditya Polepeddi

Aditya Sundar

Rejin Raveendranath Kanjavalappil

A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.

Linear low side recycling modulation

A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.

Pulse width modulated amplifier

A system and method for performing speaker load diagnostics. A digital signal processor generates a diagnostic tone that is provided to the speaker. The diagnostic tone is generated using an oscillator internal to the digital signal processor. The digital signal processor receives current and voltage data from the speaker based on the diagnostic tone, and processes the current and voltage data to determine whether a fault condition exists in the speaker.

Speaker load diagnostics

A circuit comprises a sensing resistor with a resistance Rs, a first amplifier circuit with a first gain factor G, a second amplifier circuit with a second gain factor (1/A), a third amplifier circuit, a current mirror, a buffer, and a peak voltage detector. The first amplifier circuit is coupled to the sensing resistor at a first node and a second node and to the second amplifier circuit, which is further coupled to the current mirror. The buffer is coupled to the current mirror and to the third amplifier circuit, which is further coupled to the peak voltage detector and configured to receive a voltage across a load and a voltage on a ground node. In some implementations, the load is a speaker. In some implementations, a filter is coupled between the first and the second amplifier circuits.

Analog based speaker thermal protection in class-D amplifiers

A boosted audio amplifier system includes a first digital interpolation filter configured to oversample an audio input signal at a first oversampling rate and includes a signal level detector having an input coupled to receive the oversampled audio input signal and configured to produce an audio input level signal. The system further includes a programmable delay buffer having inputs coupled to receive the oversampled audio input signal and a first delay signal. The programmable delay buffer adds a first delay to the oversampled audio input signal to produce a delayed input signal. The system also includes a first processor having inputs coupled to receive a battery voltage level signal, the audio input level signal and the first delay signal. The first processor is configured to produce boost control signals to regulate a boost voltage.

Control system for regulation of boosted audio amplifier

In some examples, an amplifier comprises a first integrator to receive a differential input signal, a second integrator coupled to the first integrator, a third integrator coupled to the second integrator, and a comparator to receive outputs of the second and third integrators, to compare each of the outputs to a reference signal that is below a power supply rail voltage supplied to the amplifier, and to produce an error current based on the comparison. The amplifier also comprises a feedback connection between the comparator and inputs to the second integrator. The feedback connection injects the inputs to the second integrator with a current that is determined at least in part by the error current.

Amplifier error current based on multiple integrators

A system includes a class D amplifier and a current steering digital-to-analog converter (DAC) directly connected to the class D amplifier. The system also includes a common mode servo circuit coupled to a node interconnecting the current steering DAC to the class D amplifier. The common servo circuit amplifies a difference between a common mode signal determined from the node and a reference voltage and generates a feedback current to the node based on the amplified difference. A feed-forward common-mode compensation circuit is included to reduce an alternating current (AC) ripple from the class D amplifier. The feed-forward common-mode compensation circuit includes first and second resistors coupled to respective outputs of the class D amplifier. A current mirror is coupled to the first and second resistors and is configured to sink a current from the node to ground that approximates a common mode feedback current of the class D amplifier.

Direct current mode digital-to-analog converter to class D amplifier

A power supply, comprising a controller comprising a first switch coupled between a first node and a second node, a first resistor coupled between the second node and a third node, a second resistor coupled between the first node and a fourth node, a capacitor coupled between the fourth node and a fifth node, an amplifier coupled at a first input to the fourth node, at a second input to the third node, and at an output to the fifth node, and a comparator coupled at a first input to the fifth node and at a second input to the third node.

Power converter controller

An amplifier includes a first transistor coupled to a first voltage source node and a second transistor coupled to a second voltage source node. The first and second transistors also couple together at an intermediate node. The amplifier further includes a third transistor coupled to the intermediate node and a fourth transistor coupled to the third transistor at a positive output node of the amplifier. Further, the amplifier includes a fifth transistor coupled to the intermediate node and a sixth transistor coupled to the fifth transistor at a negative output node of the amplifier.

Multi-level class D amplifier

A system includes an audio amplifier, a duty cycle detector, a channel equalizer, and a sample-and-hold circuit. The audio amplifier is configured to amplify an analog audio signal to produce an amplified audio signal. The duty cycle detector is configured to generate a saturation detect signal at a first state upon detection that the amplified audio signal produced by the audio amplifier is clipped. The channel equalizer is configured to generate an initial estimate of a speaker terminal voltage. The sample-and-hold circuit is configured to sample and hold the initial estimate of the speaker terminal voltage as a final estimate of the speaker voltage when the saturation detect signal is in the first state.

Growing community of inventors

Bengaluru, India

Jasjot Singh Chadha