Texas Instruments Corporation

Jarvis Benjamin Jacobs

Binghua Hu

Sameer P Pendharkar

Hiroaki Niimi

Seetharaman Sridhar

Pinghai Hao

Abbas Ali

Reima Tapani Laaksonen

Ajith Varghese

Mark Stephen Rodder

Theodore Warren Houston

Henry Litzmann Edwards

Scott William Jessen

Deborah J Riley

John P Erdeljac

Yuanning Chen

Ashesh Parikh

Sopa Chevacharoenkul

Yin Hu

Karen H R Kirmse

Stephanie Leanne Hilbun

Britton Robbins

Keeho Kim

Ronald Chin

A method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer. An etch forms a plurality of deep trenches (DTs) within the first region. A liner oxide is formed that lines the DTs. The silicon nitride layer is etched forming an opening through the silicon nitride layer that is at least as large in area as the area of an opening in the semiconductor surface of the DT below the silicon nitride layer. The liner oxide is removed, a dielectric layer(s) on a surface of the DTs is formed, a top plate material layer is deposited to fill the DTs, and the top plate material layer is removed beyond the DT to form a top plate.

Integrated trench capacitor with top plate having reduced voids

An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

High voltage CMOS with triple gate oxide

A method to fabricate a transistor comprises: forming a first dielectric layer on a semiconductor substrate; depositing a barrier layer on the first dielectric layer; depositing an anti-reflective coating on the barrier layer; depositing and exposing a pattern in a photoresist layer to radiation followed by etching to provide an opening; etching a portion of the anti-reflective coating below the opening; etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; providing an ambient oxidizing agent to grow an oxide region followed by removing the barrier layer; implanting dopants into the semiconductor substrate after removing the barrier layer; removing the first dielectric layer after implanting dopants into the semiconductor substrate; and forming a second dielectric layer after removing the first dielectric layer, wherein the oxide region is grown to be thicker than the second dielectric layer.

Method of fabricating transistors, including ambient oxidizing after etchings into barrier layers and anti-reflecting coatings

A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.

Poly sandwich for deep trench fill

A semiconductor device with a buried layer has a deep trench structure abutting the buried layer and a self-aligned sinker along sidewalls of the deep trench structure. The semiconductor device may be formed by forming a portion of a deep trench down to the buried layer, and implanting dopants into a substrate of the semiconductor device along sidewalls of the deep trench, and subsequently forming a remainder of the deep trench extending below the buried layer. Alternatively, the semiconductor device may be formed by forming the deep trench to extend below the buried layer, and subsequently implanting dopants into the substrate of the semiconductor device along sidewalls of the deep trench.

Deep trench with self-aligned sinker

A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.

Transistor performance using a two-step damage anneal

The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate structure () over a substrate (), the gate structure () including a gate electrode () located over a nitrided gate dielectric (), and forming a nitrided region () over a sidewall of the nitrided gate dielectric ().

Method for manufacturing a semiconductor device using a nitrogen containing oxide layer

The present invention provides a method for manufacturing a semiconductor device, which includes forming a gate structure over a substrate, and forming a stack of layers on the substrate and at least partially along a sidewall of the gate structure. In this embodiment, the stack of layers includes an initial layer located over the substrate, a buffer layer located over the initial layer and an offset layer located over the buffer layer. This embodiment of the method further includes removing horizontal segments of the offset layer and the buffer layer using a dry etch and a wet clean, wherein removing includes choosing at least one of an initial thickness of the buffer layer, a period of time for the dry etch or a period of time for the wet clean such that horizontal segments of the initial layer are exposed and substantially unaffected after the dry etch and wet clean.

Method for manufacturing a semiconductor device having improved across chip implant uniformity

A method () for generating an optical proximity correction model for a mask layout having an asymmetric feature structure includes fabricating a mask () having a plurality of symmetric and asymmetric test structures thereon, and image processing one or more semiconductor wafers () using the fabricated mask to create a plurality of symmetric and asymmetric resist structures overlying the one or more wafers. At least one critical dimension of the symmetric resist structures and the asymmetric resist structures are measured (), thereby generating symmetric and asymmetric critical dimension data, and a difference between a desired feature size of the symmetric and asymmetric structures and the measured feature size of the symmetric and asymmetric structures is evaluated () in order to generate an optical proximity correction model () based thereon.

Growing community of inventors

Murphy, TX, United States of America

Jarvis Benjamin Jacobs